Phytec L-827e.A3 phyCORE-i.MX 6UL/ULL, Hardware Manual, Page: 34 / 69

L-827e.A3 phyCORE-i.MX 6UL/ULL Hardware Manual
© PHYTEC Messtecknik GmbH 34
TABLE 9: Jumper Settings
Jump
er Description Type Secti
on
J10 J10 configures the chip to enable signal E1 of the serial memory at U3. In the high-
nibble of the address, I
2
C memory devices have the slave ID 0x5. The low nibble of
the address for the memory area, as well as for the additional ID page is defined
with the chip enable signals E2, E1, E0, and the R/W bit.
0 Ω
(0402)
EEPR
OM
Write
Prote
ction
Contr
ol
(R102
)
2+3 E0 = 0, E1 = 1, E2= 0, => 0x2 / 0x3 (W/R) are selected as the low-nibble of the
EEPROM's address
→
I
2
C memory address 0x52; ID page address 0x5A
1+2 E0 = 0, E1 = 0, E2= 0, => 0x0 / 0x1 (W/R)
→ I
2
C memory address 0x50; ID page address 0x58
J11 J11 selects the signals which are connected to phyCORE-Connector pin 74 and to
USER_LED. It is changeable for the G3 controller version where GPIO5_4 can not
be used as GPIO.
2x 0 Ω
(0402)
Unive
rsal
Async
hrono
us
Interf
ace
and
User
LED
1+4,
2+3 Pin 74 = GPIO1_8 (UART5_RTS_B)
USER_LED = SNVS_TAMPER4 (GPIO5_4)
1+2,
3+4 Pin 74 = SNVS_TAMPER4 (GPIO5_4)
USER_LED = GPIO1_8 (UART5_RTS_B)