L-827e.A3 phyCORE-i.MX 6UL/ULL Hardware Manual
© PHYTEC Messtecknik GmbH
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16 Display Interface
16.1 Parallel Display Interface
The signals from the LCD interface of the i.MX 6UL/ULL are brought out at the phyCORE
‑
Connector X1. Thus an LCD
display with up to 24-bit bus width can be connected directly to the phyCORE
‑
i.MX 6UL/ULL. The table below shows
the location of the applicable interface signals.
TABLE 29: Parallel Display Interface Signal Location
Pin #
Signal
ST
Voltage Domain
Description
20
X_LCD_ENABLE
O
VDD_3V3
LCD enable
21
X_LCD_CLK
O
VDD_3V3
LCD clock
22
X_LCD_VSYNC
O
VDD_3V3
LCD vertical sync
23
X_LCD_RESET
O
VDD_3V3
LCD reset
24
X_LCD_HSYNC
O
VDD_3V3
LCD horizontal sync
25
X_LCD_D0
O
VDD_3V3
LCD data 0
26
X_LCD_D1
O
VDD_3V3
LCD data 1
27
X_LCD_D2
O
VDD_3V3
LCD data 2
28
X_LCD_D3
O
VDD_3V3
LCD data 3
29
X_LCD_D4
O
VDD_3V3
LCD data 4
30
X_LCD_D5
O
VDD_3V3
LCD data 5
31
X_LCD_D6
O
VDD_3V3
LCD data 6
32
GND
-
-
Ground 0 V
33
X_LCD_D7
O
VDD_3V3
LCD data 7
34
X_LCD_D8
O
VDD_3V3
LCD data 8
35
X_LCD_D9
O
VDD_3V3
LCD data 9
36
X_LCD_D10
O
VDD_3V3
LCD data 10