Phytec L-827e.A3 phyCORE-i.MX 6UL/ULL, Hardware Manual, Page: 28 / 69

L-827e.A3 phyCORE-i.MX 6UL/ULL Hardware Manual
© PHYTEC Messtecknik GmbH 28
TABLE 7: Pinout of the phyCORE-Connector (Side 4)
Pin # Signal (pad name) ST Voltage
domain Description
Side 4
94 VDD_SNVS PWR_
I 3.3 V
Backup voltage supply input
[8]
95 X_GPIO5_5 I/O VDD_3V3
GPIO5_5
[6]
96 X_GPIO1_1 I/O VDD_3V3 GPIO1_1
97 X_USB_OTG1_ID I VDD_3V3 USB OTG1 ID pin
98 X_nRESET_OUT O VDD_SNVS Reset output (low active)
99 X_ONOFF I VDD_SNVS i.MX 6UL/ULL ONOFF (Button) input
100 X_nRESET_IN I VDD_3V3 Reset input (low active)
101 X_SNVS_PMIC_ON_RE
Q O VDD_SNVS PMIC On Request
102 X_PMIC_STBY_REQ O VDD_SNVS PMIC Standby Request
103 X_BOOT_MODE1 I VDD_SNVS Boot mode input 1
104 X_BOOT_MODE0 I VDD_SNVS Boot mode input 0
105 X_UART1_RX I VDD_3V3 UART1 serial data receive
106 X_GPIO1_18 O VDD_3V3 GPIO1_18
107 X_UART1_TX O VDD_3V3 UART1 serial data transmit
108 X_nSD1_CD I VDD_3V3 SD1 card detect (low active)
109 X_ECSPI3_CLK I/O VDD_3V3 ECSPI3 clock
110 X_ECSPI3_MOSI I/O VDD_3V3 ECSPI3 master output / slave input
111 X_ECSPI3_SS0 I/O VDD_3V3 ECSPI3 chip select 0