Phytec L-827e.A3 phyCORE-i.MX 6UL/ULL, Hardware Manual, Page: 45 / 69

L-827e.A3 phyCORE-i.MX 6UL/ULL Hardware Manual
© PHYTEC Messtecknik GmbH 45
10 SD/MM Card Interfaces
The phyCORE bus features two SD / MM Card interfaces. On the phyCORE
‑
i.MX 6UL/ULL the interface signals extend
from the controllers first and second Ultra Secured Digital (uSDHC1 / uSDHC2) Host Controller to the phyCORE-
Connector.
The table below shows the location of the different interface signals on the phyCORE-Connector. The MMC/SD/SDIO
Host Controller is fully compatible with the SD Memory Card Specification 3.0 and SD I/O Specification version 3.0.
SDC / MMC interface SD2 (uSDHC2 of the i.MX 6UL/ULL), supports 8 data channels and SD1 (uSDHC1 of the i.MX 6UL/
ULL) 4 data channels. Both interfaces have a maximum data rate of up to 104 MB/s (refer to the
i.MX 6UL/ULL
Reference Manual for more information).
TABLE 16: Location of the SD / MM Card Interface Signals
Pin # Signal ST Voltage Domain Description
6 X_SD1_CLK O VDD_3V3 uSDHC1 clock
7 X_SD1_CMD O VDD_3V3 uSDHC1 command
8 X_SD1_D0 I/O VDD_3V3 uSDHC1 data 0
9 X_SD1_D1 I/O VDD_3V3 uSDHC1 data 1
10 X_SD1_D2 I/O VDD_3V3 uSDHC1 data 2
11 X_SD1_D3 I/O VDD_3V3 uSDHC1 data 3
108 X_nSD1_CD I VDD_3V3 uSDHC1 card detection
44 X_LCD_D18 O VDD_3V3
uSDHC2 command
[13]
45 X_LCD_D19 O VDD_3V3
uSDHC2 clock
[13]
46 X_LCD_D20 I/O VDD_3V3
uSDHC2 data 0
[13]
47 X_LCD_D21 I/O VDD_3V3
uSDHC2 data 1
[13]
48 X_LCD_D22 I/O VDD_3V3
uSDHC2 data 2
[13]
49 X_LCD_D23 I/O VDD_3V3
uSDHC2 data 3
[13]
40 X_LCD_D14 I/O VDD_3V3
uSDHC2 data 4
[13]