L-827e.A3 phyCORE-i.MX 6UL/ULL Hardware Manual
© PHYTEC Messtecknik GmbH
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11.6.2 SPDIF
The Sony/Philips Digital Interface (SPDIF) audio block is a stereo transceiver that allows the processor to receive
and transmit digital audio. The following table shows the location of the SPDIF output signal on the
phyCORE
‑
Connector.
TABLE 24: SPDIF Interface Signal Location
Pin #
Signal
ST
Voltage Domain
Description
81
X_JTAG_MOD
O
VDD_3V3
SPDIF transmit
11.7 CAN Interface
The CAN interface of the phyCORE
‑
i.MX 6UL/ULL is connected to the first FLEXCAN module (FLEXCAN1) of the
i.MX 6UL/ULL which is a full implementation of the CAN protocol specification version 2.0B. It supports standard
and extended message frames and programmable bit rates of up to 1 Mb/s.
The following table shows the position of the signals on the phyCORE
‑
Connector.
TABLE 25: CAN Interface Signal Location
Pin #
Signal
ST
Voltage Domain
Description
86
X_SNVS_TAMPER2
O
VDD_3V3
GPIO5_2 (CAN enable)
113
X_FLEXCAN1_RX
I
VDD_3V3
FLEXCAN 1 receive
114
X_FLEXCAN1_TX
O
VDD_3V3
FLEXCAN 1 transmit
Note
Use of the i.MX 6UL/ULL's JTAG_MOD pin as SPDIF output is the default muxing option within the BSP
delivered with the phyCORE
‑
i.MX 6UL/ULL. Please refer to the
i.MX 6UL/ULL Reference Manual
for more
muxing options about this interface or consider that fact in the carrier board design if a JTAG interface is
also to be implemented.
Note
The CAN interface is not available on the processor type -G0 and -Y0.