L-827e.A3 phyCORE-i.MX 6UL/ULL Hardware Manual
© PHYTEC Messtecknik GmbH
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X_JTAG_TDI/
SAI2_TX_BCLK
O
VDD_3V3
transmit bit clock
80
X_JTAG_TCK/SAI2_RXD
I
VDD_3V3
receive data
81
X_JTAG_MOD
O
VDD_3V3
SPDIF output line signal
82
X_JTAG_TDO/
SAI2_TX_SYNC
O
VDD_3V3
transmit frame sync
83
X_JTAG_TMS/SAI2_MCLK
O
VDD_3V3
master clock
84
X_nJTAG_TRST_B/
SAI2_TXD
O
VDD_3V3
transmit data
85
X_GPIO5_3
I
VDD_SNVS
GPIO5_3
86
X_GPIO5_2
O
VDD_SNVS
GPIO5_2 (CAN enable)
87
X_GPIO5_1
I
VDD_SNVS
GPIO5_1
88
X_GPIO5_0
I
VDD_SNVS
GPIO5_0
89
GND
-
-
Ground 0 V
90
VDD_3V3
PWR_I
3.3 V
3.3 V primary voltage supply input
91
VDD_3V3
PWR_I
3.3 V
3.3 V primary voltage supply input
92
VDD_3V3
PWR_I
3.3 V
3.3 V primary voltage supply input
93
VDD_3V3
PWR_I
3.3 V
3.3 V primary voltage supply input