L-827e.A3 phyCORE-i.MX 6UL/ULL Hardware Manual
© PHYTEC Messtecknik GmbH
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The above values are to be seen as an orientation for dimensioning the power supply of the SOM. In order to ensure
the proper functionality of the SOM, we recommend that the power supply is design to provide approximately 20 %
higher currents. We also recommend that the final application is revalidated in regards to adequate current supply
using application-specific use case scenarios.
6.2 Voltage Regulator (U4)
The phyCORE-i.MX 6UL/ULL provides an on-board dual output step-down DC-to-DC converter at position U4 to
generate two voltages required by the microcontroller and the on-board components.
6.3 Power Domains
External voltages:
VDD_3V3
3 V main supply voltage
X_USB_OTG1_VBUS
USB1 Bus voltage must be supplied with 5 V if USB1 is used
X_USB_OTG2_VBUS
USB2 Bus voltage must be supplied with 5 V if USB2 is used
VDD_SNVS
Backup supply (isolated from VDD_3V3 by diode D1)
Internally generated voltages: VDD_ARM_SOC (1.4 V, 1.3 V, 0.925) and VDD_DDR3_1V35 (1.35 V).
VDD_ARM_SOC
i.MX 6UL/ULL Core and SOC voltage is switchable from 1.4 V to 1.3 V and 0.925 V
VDD_DDR3_1V35
(1.35 V)
i.MX 6UL/ULL DDR interface (NVCC_DRAM), RAM devices 1.3 V and 0.925 V
VDD_SNVS
(3.3 V)
i.MX 6UL/ULL backup supply (isolated from VDD_3V3 over by
VDD_3V3
(3.3 V)
i.MX 6UL/ULL pad supply (VDD_HIGH_IN, VDD_ADC_3P3NVCC,
ADC_VREFH, NVCC_UART, NVCC_NAND, NVCC_SD1, NVCC_GPIO,
NVCC_LCD, NVCC_CSI, NVCC_ENET), Voltage supervisor, I
2
C EEPROM, NAND Flash,
Ethernet PHY
Warning
As a general design rule, we recommend connecting all GND pins neighboring signals which are being used
in the application circuitry. For maximum EMI performance, all GND pins should be connected to a solid
ground plane.