L-827e.A3 phyCORE-i.MX 6UL/ULL Hardware Manual
© PHYTEC Messtecknik GmbH
48
75
X_UART5_CTS_B
O
VDD_3V3
UART5 serial clear to send output (low
active, usually used as RTS)
74
X_UART5_RTS_B
I
VDD_3V3
UART5 serial request to send input (low
active, usually used as CTS)
11.2 USB OTG/Host Interfaces
The phyCORE
‑
i.MX 6UL/ULL provides two high-speed USB OTG/host interfaces that use the i.MX 6UL/ULL embedded
HS USB PHY. An external USB Standard-A (for USB host), USB Standard-B (for USB device), or USB mini-AB (for USB
OTG) connector is all that is needed to interface the phyCORE
‑
i.MX 6UL/ULL USB OTG/host functionality. The
applicable interface signals can be found on the phyCORE
‑
Connector X1 as shown below. Please note that USB2 is
not available on the processor type -G0 and -Y0.
TABLE 18: Location of the USB OTG/Host Signals
Pin #
Signal
ST
Voltage Domain
Description
97
X_USB_OTG_ID
I
VDD_3V3
USB OTG1 ID Pin
65
X_USB_OTG1_D-
USB_I/O
i.MX 6UL internal
USB OTG1 data-
66
X_USB
USB_I/O
i.MX 6UL internal
USB OTG1 data+
67
X_USB_OTG1_VBUS
PWR_I
5 V
USB OTG1 VBUS input
68
X_USB_OTG1_CHD_B
OC
i.MX 6UL internal
USB OTG1 charger
detection
69
X_USB_OTG2_D-
USB_I/O
i.MX 6UL internal
USB OTG2 data-
70
X_USB
USB_I/O
i.MX 6UL internal
USB OTG2 data+
71
X_USB_OTG2_VBUS
PWR_I
5 V
USB OTG2 VBUS input
76
X_USB_OTG2_ID
I
VDD_3V3
USB OTG2 ID Pin
Warning
X_USB_OTG_VBUS must be supplied with 5 V for proper USB functionality.