Phytec L-827e.A3 phyCORE-i.MX 6UL/ULL, Hardware Manual, Page: 61 / 69

L-827e.A3 phyCORE-i.MX 6UL/ULL Hardware Manual
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17.1 Parallel Camera Interface (CSI)
The camera parallel interface CSI is available at the phyCORE ‑ Connector with 10 data bits, HSYNC, VSYNC, MCLK,
PIXCLK, and I²C Bus . The following table shows the location of the parallel CSI camera signals at the
phyCORE ‑ Connector.
TABLE 31: Parallel Camera Interface CSI Signal Location
Pin # Signal ST Voltage Domain Description
115 X_CSI_D0 I VDD_3V3 CSI data 0
116 X_CSI_D1 I VDD_3V3 CSI data 1
117 X_CSI_D2 I VDD_3V3 CSI data 2
118 X_CSI_D3 I VDD_3V3 CSI data 3
119 X_CSI_D4 I VDD_3V3 CSI data 4
120 X_CSI_D5 I VDD_3V3 CSI data 5
121 X_CSI_D6 I VDD_3V3 CSI data 6
122 X_CSI_D7 I VDD_3V3 CSI data 7
123 X_CSI_D8 I VDD_3V3 CSI data 8
124 X_CSI_D9 I VDD_3V3 CSI data 9
2 X_CSI_VSYNC I VDD_3V3 CSI vertical sync
3 X_CSI_HSYNC I VDD_3V3 CSI horizontal sync
4 X_CSI_PIXCLK O VDD_3V3 CSI pixel clock
5 X_CSI_MCLK O VDD_3V3 CSI Camera MCLK
Signals that can be optionally be used with the camera ports
60 X_I2C1_SCL OC_BI VDD_3V3 I2C1 clock
61 X_I2C1_SDA OC_BI VDD_3V3 I2C1 data