L-827e.A3 phyCORE-i.MX 6UL/ULL Hardware Manual
© PHYTEC Messtecknik GmbH
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14 Debug Interface
The phyCORE
‑
i.MX 6UL/ULL is equipped with a JTAG interface for downloading program code into the external
flash, internal controller RAM, or for debugging programs currently executing.
The table below shows the location of the JTAG pins on the phyCORE-Connector X1.
TABLE 27: Debug Interface Signal Location at phyCORE
‑
Connector X1
Pin #
Signal
ST
Voltage Domain
Description
83
X_JTAG_TMS/SAI2_MCLK
I
VDD_3V3
JTAG TMS
82
X_JTAG_TDO/SAI2_TX_SYNC
O
VDD_3V3
JTAG TDO
80
X_JTAG_TCK/SAI2_RXD
I
VDD_3V3
JTAG clock input
84
X_JTAG_TRSTB/SAI2_TXD
I
VDD_3V3
JTAG reset input (low active)
79
X_JTAG_TDI/SAI2_TX_BCLK
I
VDD_3V3
JTAG TDI
81
X_JTAG_MOD
I
VDD_3V3
JTAG MOD
Note
On the phyCORE-i.MX 6UL/ULL the JTAG pins are used for other functions (SAI2 interface and SPDIF) within
the included BSP. This must be considered if a debug interface is to be implemented in addition to an
audio and/or SPDIF interface. Please refer to the
i.MX 6UL/ULL Reference Manual
for more muxing options
about this interface or consider that fact in the carrier board design.