L-827e.A3 phyCORE-i.MX 6UL/ULL Hardware Manual
© PHYTEC Messtecknik GmbH
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Write protection to the device is accomplished by a high level on signal Write Control when resistor R102 is
removed. If resistor R101 is mounted write protection can also be changed by the EEPROM_WP signal
Configuring Chip Enable Signal E1 (J10)
11.
See the manufacturer’s datasheet for interfacing and operation.
12. This feature is not available if the phyCORE-i.MX 6UL/ULL is
equipped with the i.MX 6UL version G3 supporting tamper detection.
9.3.1 Configuring Chip Enable Signal E1 (J10)
The 4 kB I²C EEPROM populating U3 on the phyCORE-i.MX 6UL/ULL module has the capability of configuring the
address for the memory area and the additional ID page using chip-enabled signals E0 to E2. The four upper address
bits of the device are fixed at ‘1010’ (see M24C32 datasheet). Chip enable signals E0 and E2 are fixed connected to
GND. The remaining chip enables signal E1 is configurable using jumper J10.
The table below shows the resulting seven-bit I²C memory area and ID page address for the two possible jumper
configurations.
TABLE 14: U3 EEPROM I²C Addresses via J10
U3 I²C Addresses
J10
memory address 1010 000 (0x50)
ID page address 0x58
1 + 2
memory address 1010 010 (0x52)
ID page address 0x5A
2 + 3
9.3.2 EEPROM Write Protection Control (R102)
Resistor R102 controls write access to the EEPROM (U3) device. Closing this 0
Ω
jumper enables write access to the
device, while removing this resistor will cause the EEPROM to enter write-protect mode, thereby disabling write
access to the device.
The following configurations are possible:
TABLE 15: EEPROM Write Protection States via R10217
EEPROM Write Protection State
R102
Write access allowed
closed
EEPROM is write-protected.
The protection can be changed by the EEPROM_WP signal (GPIO5_6) if R101 is
populated
open
9.4 eMMC (U12)
If the eMMC Module is used with PL1515 the second usdhc2 interface is not available for other functionalities.