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30
Comparison with the CPM2C
Section 1-5
Differences in I/O Memory
IR Area Differences
AR Area Differences
Battery
Battery
Internal lithium battery backup
CPU Unit with clock:
Internal lithium battery backup
CPU Unit without clock: Capacitor
backup or optional lithium battery
backup
Battery replace-
ment
Possible
Possible
Life expectancy/
backup time
2-year lifetime at 25
°
C
CPU Unit with clock: 2-year lifetime at
25
°
C
CPU Unit without clock (capacitor): 10-
day backup at 25
°
C
CPU Unit without clock (lithium
battery): 5-year lifetime at 25
°
C
Battery error detec-
tion
Supported.
Supported.
Communications
(in CPU Unit)
Peripheral port (via
communications
port)
Programming Console
(Set with Communications Switch.)
Peripheral bus
(Set with Communications Switch.)
Host Link (with Slave-initiated
communications)
No-protocol
Programming Console
(Set with Communications Switch.)
Peripheral bus
(Set with Communications Switch.)
Host Link (with Slave-initiated
communications)
No-protocol
RS-232C port (via
communications
port)
Peripheral bus (Set with
Communications Switch.)
Host Link
No-protocol
1:1 PC LInk
1:1 NT Link
Peripheral bus (Set with
Communications Switch.)
Host Link
No-protocol
1:1 PC LInk
1:1 NT Link
Input time constant
Can be set to 1, 2, 3, 5, 10, 20, 40, or
80 ms. (Default: 10 ms)
Can be set to 1, 2, 3, 5, 10, 20, 40, or
80 ms. (Default: 10 ms)
Function
CPM2C-S
CPM2C
CompoBus/S input bits
IR 020 to IR 027
---
CompoBus/S output bits
IR 030 to IR 037
Work bits
672 bits:
IR 028 to IR 029
IR 038 to IR 049
IR 200 to IR 227
928 bits:
IR 028 to IR 049
IR 200 to IR 227
Item
CPM2C-S
CPM2C
Function
CPM2C-S
CPM2C
DeviceNet Status
AR 00
---
CompoBus/S Active Slave Flags
and Communications Error Flags
AR 04 to AR 07
CompoBus/S Master ASIC Error
AR 1315
Summary of Contents for CPM2C-S100C
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Page 180: ...158 One to one PC Link I O Response Time Section 7 4 ...
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