Oki MSM66591, User Manual

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MSM66591/ML66592 User's Manual
Chapter 3 CPU Architecture
[2] Table Segment Register (TSR)
TSR specifies the segment (in the program memory space) to which the table data
belongs. TSR is an 8-bit register which is assigned to the SFR area.
TSR can be read/written by the program. Data in the table segment can be accessed
using the ROM reference instructions (LC, LCB, CMPC, and CMPCB). By executing the
ROM window function, RAM addressing can be used for this table segment.
In MSM66591, only bit 0 of TSR is valid. If a read instruction is executed, "0s" are read
from bits 1 to 7. Since in the MSM66591 TSR has only one valid bit while on the
emulator for the MSM66591 TSR has two valid bits, be sure to write "0s" to bits 1 to 7
when writing to TSR.
In ML66592, only bits 0 and 1 of TSR are valid. If a read instruction is executed, "0s"
are read from bits 2 to 7. Since in the ML66592 segment 3 is not provided, do not
access segment 3. When writing to TSR, be sure to write "0s" to bits 2 to 7.
Each segment is assigned offset addresses of 0 through 0FFFFH. The address calcula-
tion for determining the addressing target is performed by a 16-bit offset address, and
the resulting overflow and underflow are ignored, which therefore never results in a
change in TSR. The TSR value at reset is 00H.
"0" "0" "0" "0" "0" "0" "0" (MSM66591)
(ML66592)
7 6 5 4 3 2 1 0
TSR
"0" "0" "0" "0" "0" "0"
7 6 5 4 3 2 1 0
TSR