Oki MSM66591, User Manual

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MSM66591/ML66592 User's Manual
Chapter 15 Serial Port Functions
15.3.2 Receive Operation
The UART mode used by the SCI0, SCI2, SCI3, and SCI4 serial ports on the receive
side has a single buffer mode and a 4-stage buffer mode. Single buffer mode has a
single stage of receive buffer, and 4-stage buffer mode has four stages of receive
buffers. SCI1 has single buffer mode only.
[1] Single Buffer Mode
<UART Normal Mode>
The clock pulse (BRGn), generated by the baud rate generator (SnTM), is divided by 16
to generate the receive shift clock (SRnCLK) (refer to Figure 15-33). The 1/16 dividing
circuit stops in reset status until the receive operation starts.
The 7th, 8th and 9th pulses of the 1/16 division become the input sampling clock of the
RXDn pin, and the 10th pulse becomes SRnCLK. The receive circuit controls the
fetching of the receive data, synchronizing with SRnCLK.
The receive operation is started (SRnREN of SRnCON must be "1" at this time) when
the RXDn pin is changed from "H" to "L" level, and the SRnFREE signal that indicates
receiving is set to "L" level.
When SRnFREE becomes "L" level, the 1/16 dividing circuit, that has been stopped in
reset status, operates, and the start bit ("L" level) is sampled by 3 sampling clocks of
the 1/16 division (7th, 8th and 9th). If 2 or more sampling clocks are in "L" level, the
start bit is judged as valid, and the receive operation continues. If 2 or more sampling
clocks are in "H" level, the start bit is judged as invalid, and the receive operation is
initialized (SRnFREE becomes "H" level), and then stops.
Receive data is sampled by 3 sampling clocks of the 1/16 division (7th, 8th and 9th),
and 2 or more values of the sampled values are shifted in to the receive register as
receive data by the 10th pulse (SRnCLK).
Hereafter, receive data continues to be received according to the specification of
SRnCON. The stop bit is received, the receive operation ends, and the LSRnBUF
signal is generated.
The receive operation ends when the first stop bit is detected, regardless of whether the
stop bit of the receive data is 1 bit or 2 bits.
If LSRnBUF is generated, the content of the receive register (receive data) is trans-
ferred to SnBUF, an overrun error, framing error and parity error (if parity bit exists) are
set, a receive interrupt request signal (RXnREADY) is generated synchronizing with the
M1S1 signal, which indicates the beginning of an instruction, and the interrupt request
flag (QSCIn) is set to "1".
<UART Multiprocessor Communication Mode>
In UART multiprocessor communication mode, receive is controlled by the same timing
as UART normal mode. The differences are shown below.
• Setting of multiprocessor communication error
• If SRnMPC of SRnCON is "0", receive data is accepted regardless of the MPC bit of
the receive data. When SRnMPC of SRnCON is "1", receive data is accepted if the
MPC bit of receive data is "1", but receive data is not accepted if the MPC bit of
receive data is "0". This means that data shifted in the shift register will not be loaded
to SnBUF, and also that an interrupt request will not be generated.
[Note] n = 0–4.