Oki MSM66591, User Manual

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13-16
MSM66591/ML66592 User's Manual
Chapter 13 PWM Functions
13.2 Operation of PWM
PWM0–PWM11 control duty within a specific cycle (determined by the count clock of
PWC0–PWC11 or by the contents of PWC0–PWC11 and PWC0BF–PWC11BF).
PWM is started by setting the corresponding RUN bit to "1". If the RUN bit becomes "1",
the output F/F is set to "1" at the same time, and "H" level is output to the PWM output
pin (in the case of high active status.) If the contents of the corresponding PWC0–
PWC11 and PWR0–PWR11 match, the output F/F is set to "0", "L" level is output to the
PWM output pin and an individual interrupt request flag is set to "1". If PWC0–PWC11
generate an underflow, the output F/F is set to "1", "H" level is output to the PWM
output pin, an individual interrupt request flag is set to "1", and, at the same time, the
contents of PWC0BF–PWC11BF and PW0BF–PW11BF are loaded to PWC0–PWC11
and PWR0–PWR11, respectively. This operation is repeated, and the duty-controlled
waveform is output from the PWM output pin until the RUN bit is set to "0".
If an underflow of PWC0–PWC11 and a match of the contents of PWC0–PWC11 and
PWR0–PWR11 occur concurrently (when PWR = 0000H is set), the interrupt request by
an underflow of PWC0–PWC11 is given priority. Therefore, only the individual interrupt
request flag by the underflow of PWC0–PWC11 is set to "1"; the individual interrupt
request flag by the match of the contents of PWC0–PWC11 and PWR0–PWR11 is not
set to "1".
The duty immediately after PWM start may become shorter (only 1 cycle), depending
on the selected count clock of PWC0–PWC11. Refer to the following example.
Maximum Errors
TBCCLK –(TBCCLK – 1 CLK)
1/2 TBCCLK –(1/2 TBCCLK – 1 CLK)
1/4 TBCCLK
1/8 TBCCLK
0
–(1/4 TBCCLK – 1 CLK)
–(1/8 TBCCLK – 1 CLK)
Master Clock (CLK)
Count Clock
1/16 TBCCLK –(1/16 TBCCLK – 1 CLK)
1/32 TBCCLK –(1/32 TBCCLK – 1 CLK)
If a different clock is used for the PWC clock with the equal value set for PWCn and
PWCnBF (n = 0–11) and PWnRUN bit is set to "1" at the same time, the cycle will be
equal, however a synchronization shift may occur.
If the PWCn and PWCnBF (n = 0–11) values are both FFFFH, and in high active status,
PWM becomes 1/65536 duty output when PWR is FFFFH. If the PWR value is de-
creased, the output duty ("H" level period) increases. If the PWR value is 0000H, output
becomes 65536/65536 at 100% duty. 0/65536, which is 0% duty, cannot be imple-
mented in a PWM block.