Oki MSM66591, User Manual

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12-6
MSM66591/ML66592 User's Manual
Chapter 12 General-Purpose 8-Bit Timer Function
12.2 General-Purpose 8-Bit Event Counter (GEVC)
The general-purpose 8-bit event counter consists of an 8-bit counter (GEVC), and an 8-
bit general-purpose 8-bit timer control register (GTMCON) that controls operations.
Figure 12-4 shows the configuration of GEVC.
General-purpose 8-bit timer interrupts and general-purpose 8-bit event counter inter-
rupts are assigned to the same interrupt vector. Indication of whether each individual
interrupt request has been generated or not and whether to enable or disable genera-
tion of each individual interrupt request are specified by the general-purpose 8-bit timer
interrupt control register (GTINTCON).
Figure 12-4 Configuration of GEVC
External rise
External fall
GEVC
OVF
GTMCON
Selector
Interrupt
QEVC EEVC
[Note]
When the general-purpose 8-bit counter is set to STOP mode, and when STOP mode is
cleared by an interrupt, the 8-bit event counter (GEVC) may be incremented by 1
depending on the input level of the external clock (P9_7/ECTCK pin) at that time.
[1] General-Purpose 8-Bit Event Counter (GEVC)
The GEVC is an 8-bit counter that generates an interrupt request when an overflow
occurs. The count clock of the GEVC is selected by the high-order 2 bits of the general-
purpose 8-bit timer control register (GTMCON).
At reset (when the
RES
signal is input, the BRK instruction is executed, the watchdog
timer is overflown, or an operation code trap is generated), the GEVC becomes 00H,
and the count operation stops. In STOP mode, the GEVC operates at the falling edge
of the external clock.
[2] General-Purpose 8-Bit Timer Control Register (GTMCON)
The GTMCON is an 8-bit register that counts inputs to the P9_7/ECTCK pin. It selects
the count clock of the GTMC and controls the start/stop of the count operation using the
low-order 4 bits. It also selects the count clock of the GEVC and controls the start/stop
of the count operation using the high-order 2 bits. GEVC counts inputs to the P9_7/
ECTCK pin.
At reset (when the
RES
signal is input, the BRK instruction is executed, the watchdog
timer is overflown, or an operation code trap is generated), the GTMCON becomes
30H, a 1/2 TBCCLK is selected as the count clock of the GTMC, and the count opera-
tion stops. The external clock rising edge is selected as the count clock of the GEVC,
and the count operation stops.
Figure 12-2 (page 12-4) shows the configuration of the GTMCON.