Oki MSM66591, User Manual

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15
MSM66591/ML66592 User's Manual
Chapter 15 Serial Port Functions
[3] SCI1 Transmit/Receive Buffer Register (S1BUF)
S1BUF is an 8-bit register that holds transmit/receive data during a serial port transmit/
receive operation. S1BUF has a double structure, in which the content is different in
READ/WRITE. If in read, S1BUF functions as a receive buffer, and if in write, S1BUF
functions as a transmit buffer.
When a receive operation ends, the content of the receive register is transferred to the
S1BUF receive buffer, and a receive interrupt request is generated at the same time.
The content of the S1BUF receive buffer is held until the next receive operation ends.
When receive mode is in UART/synchronous multiprocessor communication mode, if
data has been received instead of reception of an address and if the receive data is
ignored, the content of S1BUF is not updated even at completion of the receive opera-
tion, also a receive interrupt request is not generated.
The 4-stage buffer mode is not provided for SCI1.
At reset (when the
RES
signal is input, the BRK instruction is executed, the watchdog
timer is overflown, or an operation code trap is generated), S1BUF becomes undefined.
[4] SCI1 Transmit and Receive Registers
The SCI1 transmit and receive registers are two 8-bit shift registers that actually per-
form shift operations during a transmit/receive operation.
The transmit and receive registers and transmit/receive buffer register (S1BUF) have a
double structure. When a receive operation ends, the data received by the receive
register is transferred to S1BUF, and a receive interrupt request is generated.
The transmit and receive registers cannot be read/written by the program.
[5] SCI1 Status Register (S1STAT)
The high-order 4 bits of S1STAT is the transmit-ready/receive-ready interrupt request
control register of the serial port. The low-order 4 bits of S1STAT is the register that
holds the status (normal/abnormal) when the serial port receive operation is completed.
The low-order 4-bits of S1STAT are updated when receive ends. Once S1STAT is set
("1": error occurred), it is not reset to "0" even if an error does not occur when the next
receive ends. Therefore reset to "0" any bits that are "1" of the low-order 4 bits of
S1STAT by the program when a receive ends.
The contents of S1BUF must be read before resetting OERR1 (bit 1) of the low-order 4
bits of S1STAT to "0". Otherwise, the OERR1 flag is set to "1" again irrespective of
occurrence of an overrun error in next receive operation.
At reset (when the
RES
signal is input, the BRK instruction is executed, the watchdog
timer is overflown, or an operation code trap is generated), S1STAT becomes 00H.
Figure 15-11 shows the configuration of S1STAT.