Oki MSM66591, User Manual

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23-2
MSM66591/ML66592 User's Manual
Chapter 23 Serial Port with FIFO (SCI5)
23.2 SCI5 Control Register 0 (SCI5CON0)
The SCI5 control register 0 (SCI5CON0) is a 7-bit register that controls SCI5 operation.
At reset (when the
RES
signal is input, the BRK instruction is executed, the watchdog
timer is overflown, or an operation code trap is generated), SCI5CON0 becomes 10H.
Figure 23-2 shows the configuration of SCI5CON0.
<Description of Each Bit>
• S5CK0–S5CK2 (bits 0–2)
These bits select the SCI5 shift clock.
The selected shift clock is output from pin P5_2/SCLK.
• S5RES (bit 3)
This flag is used to initialize the SCI5’s FIFO pointer.
If this flag is set to "1", the FIFO pointer will be initialized. After initialization, this flag
is automatically cleared. This flag is used to initialize the FIFO pointer when commu-
nication is cut off.
• S5EXIE (bit 5)
This flag enables or disables the generation of interrupt requests by the valid edge of
external interrupt 2 (INT2).
If this bit is set to "1", the generation of interrupt requests is enabled. If set to "0", the
generation of interrupt requests is disabled.
• S5RIE (bit 6)
This flag enables or disables the generation of interrupt requests at the completion of
SCI5 reception.
If this bit is set to "1", the generation of interrupt requests is enabled. If set to "0", the
generation of interrupt requests is disabled.
• S5TIE (bit 7)
This flag enables or disables the generation of interrupt requests at the completion of
SCI5 transmission.
If this bit is set to "1", the generation of interrupt requests is enabled. If set to "0", the
generation of interrupt requests is disabled.