Oki MSM66591, User Manual

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MSM66591/ML66592 User's Manual
Chapter 15 Serial Port Functions
[8] SCI3 Status Register 2 (S3STAT2)
If the SR3EXP bit of SR3CON is set to "1" (4-stage buffer mode), the lower 3 bits of
S3STAT2 store the status (normal/abnormal) of the serial transfer when a serial port
receive operation is completed. The upper 2 bits of S3STAT2 monitor the counter that
indicates the receive buffer into which receive data will be transferred at completion of
the next receive operation.
During the 4-stage buffer mode, if there is an error in the receive data transferred to
S3BUF3, the lower 3 bits of S3STAT2 (bits 1–3) are updated when reception of that
data is complete. Once the lower 3 bits of S3STAT2 are set to "1" ("1": error occurred),
they are not reset to "0" even if that error has not occurred at completion of the next
reception. Therefore, with the program, reset to "0" any bits that are "1" of the lower 3
bits of S3STAT2 after reception is complete. Read the contents of S3BUF3 before
resetting the OERR33 flag in the lower 3 bits of S3STAT2. If the contents of S3BUF3
are not read, the OERR33 flag will be set to "1" again regardless of whether an overrun
error occurs in the next receive operation.
Bits 4 and 5 of S3STAT2 are read-only and cannot be written to. During the 4-stage
buffer mode, the next receive buffer into which data will be transferred (S3BUF0,
S3BUF1, S3BUF2, S3BUF3) can be verified by reading bits 4 and 5 of S3STAT2.
At reset (when the
RES
signal is input, the BRK instruction is executed, the watchdog
timer is overflown, or an operation code trap is generated), S3STAT2 becomes C1H.
Figure 15-22 shows the configuration of S3STAT2.
<Description of Each Bit>
• OERR33 (bit 1)
When an SCI3 receive operation is complete and the receive data is transferred into
S3BUF3, OERR33 is set to "1" if the data transferred into S3BUF3 for the previous
reception has not yet been read by the CPU. New receive data is loaded into
S3BUF3 even if OERR33 has been set. (Overrun error)
• PERR33 (bit 2)
With SCI3, the parity of data received by S3BUF3 is compared to the parity bit
appended to and transferred with the data. If they do not match, PERR33 is set to
"1". (Parity error)
• MERR33 (bit 3)
During the SCI3 UART multiprocessor communication mode, MERR33 is set to "1" if
an address is transmitted while S3BUF3 is receiving data. In other words, when the
MPC bit (of the data that is transferred when the SR3MPC bit of SR3CON is "0") is
"1", MERR33 is set to "1", interpreting this as a multiprocessor communication error.
• BFCU30 (bit 4), BFCU31 (bit 5)
During the 4-stage buffer mode, BFCU30 and BFCU31 monitor the buffer counter
that indicates the receive buffer into which receive data will be transferred (S3BUF0,
S3BUF1, S3BUF2, S3BUF3) at completion of the next receive operation. BFCU30
and BFCU31 are read-only and cannot be written to.