Oki MSM66591, User Manual

Page: 46 / 466

3-1
MSM66591/ML66592 User's Manual
Chapter 3 CPU Architecture
3
3. CPU Architecture
3.1 Memory Space
Program memory space and data memory space in MSM66591/ML66592 are set
independently. At reset, up to 64K bytes (small-sized memory model) can be accessed
for program memory space, and up to 6K bytes (MSM66591) or 8K bytes (ML66592) for
data memory space. By changing the setting of the memory size control register
allocated to the SFR, the program memory space can be expanded up to 128K bytes
(MSM66591) or 192K bytes (ML66592) (medium-sized memory model).
3.1.1 Memory Space Expansion
The memory size control register (MEMSCON) is a register allocated to the SFR area
and specifies the size of the memory space. The program memory space can be
expanded to 128K bytes (medium-sized memory model) by setting the LROM bit (bit 1)
to "1". (Write "0" to bit 0.)
To write to the LROM bit of MEMSCON, first write "5H" to the high-order 4 bits (low-
order 4 bits are arbitrary data) of the memory size accepter (MEMSACP) allocated to
the SFR area, then write "0AH" to them successively.
When an FJ or FCAL is executed with the LROM bit "0", an OP code trap is generated
and a reset occurs.
When data is written to the LROM bit (setting to "1"), an actual memory space expan-
sion is enabled after the instruction next to a LROM bit write instruction (setting to "1") is
executed.
7 6 5 4 3 2 1 0
— — — — — — LROM "0"
MEMSCON
0
1
Program Memory
Space 64K bytes
Program Memory
Space 128K bytes
*1
"—" indicates a bit that is not provided.
"1" is read if a read instruction is executed.
"0" indicates a bit that is not provided.
"0" is read if a read instruction is executed.
Always write "0" to this bit for write.
*1 192K bytes for the ML66Q592
7 6 5 4 3 2 1 0
MEMSACP
Writing to MEMSCON
is enabled by writing
"5H" and "0AH"
succesively.
— — — —