Oki MSM66591, User Manual

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14
MSM66591/ML66592 User's Manual
Chapter 14 Baud Rate Generator Functions
14.9 Configuration of SCI4 Timer (S4TM)
The SCI4 timer (S4TM) consists of an 8-bit SCI4 timer counter, an 8-bit SCI4 timer
register that stores the reload values of the SCI4 timer counter, and a control register
(S4CON) that specifies S4TM operations.
[1] SCI4 Timer Counter (low-order 8 bits of 16-bit register S4TM)
The SCI4 timer counter is an 8-bit counter. When S4TM overflows, an interrupt request
is generated, and the content of the 8-bit SCI4 timer register is loaded to SCI4 timer
counter. The count clock of S4TM is selected by the high-order 3 bits (bits 5–7) of the
8-bit SCI4 timer control register (S4CON).
[2] SCI4 Timer Register (high-order 8 bits of 16-bit register S4TM)
The SCI4 timer register is an 8-bit register. The content of the register is loaded to the
SCI4 timer counter when the counter overflows.
The SCI4 timer counter and SCI4 timer register are accessible only as a 16-bit S4TM
which uses the SCI4 timer counter as its low-order 8 bits and the SCI4 timer register as
its high-order 8 bits.
At reset (when the
RES
signal is input, the BRK instruction is executed, the watchdog
timer is overflown, or an operation code trap is generated), S4TM becomes 0000H, and
the count operation stops.
[3] SCI4 Timer Control Register (S4CON)
S4CON is an 8-bit register. The high-order 4 bits (bits 4–7) select the count clock of
S4TM, and controls the start/stop of the count operation. The low-order 2 bits (bits 2
and 3) perform interrupt related controls. The least significant bit (bit 0) specifies the
mode of S4TM.
At reset (when the
RES
signal is input, the BRK instruction is executed, the watchdog
timer is overflown, or an operation code trap is generated), S4CON becomes 02H, a
CLK is selected as the count clock of S4TM, the auto reload timer mode is selected,
and operation stops.
Figure 14-6 shows the configuration of S4CON.
<Description of Each Bit>
• S4MOD (bit 0)
This bit specifies the operation mode of S4TM. If this bit is "0", S4TM operates in
auto reload timer mode. If "1", S4TM operates in SCI4 baud rate generator mode.
• QSTM4 (bit 2)
This bit becomes "1" if an SCI4 timer counter overflow is generated. Since this bit
does not become "0" automatically after an interrupt process is executed, it is
necessary to set to "0" by the program.
• ESTM4 (bit 3)
This bit enables/disables an interrupt request generation by an SCI4 timer counter
overflow. If this bit is "1", generation is enabled, and if "0", generation is disabled.