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Oki MSM66591, User Manual

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20-6

MSM66591/ML66592 User's Manual
Chapter 20   Interrupt Request Processing Function

[1]

Interrupt Request Flag Disable Register IRQD (IRQD0L, IRQD0H, IRQD1L, IRQD1H, IRQD2L)

The IRQD is a register that enables/disables the corresponding bit of the IRQ to be set
to "1" by the interrupt signal from each interrupt generation source. If a bit of IRQD is
"1", the corresponding bit of IRQ is not set, even if the corresponding interrupt genera-
tion source generated an interrupt request. If a bit of IRQD is "0", the corresponding bit
of IRQ is set to "1" by the interrupt request from the corresponding interrupt generation
source.

At reset (when the 

RES

 signal is input, the BRK instruction is executed, the watchdog

timer is overflown, or an operation code trap is generated), IRQD0L, IRQD0H, IRQD1L,
and IRQD1H become 00H, IRQD2L becomes C0H, and enable the corresponding bit of
IRQ to be set to "1" by an interrupt signal from each interrupt generation source.

[2]

Interrupt Request Register IRQ (IRQ0L, IRQ0H, IRQ1L, IRQ1H, IRQ2L)

IRQ becomes "1" synchronizing with the M1S1 signal if an interrupt signal is generated
from each interrupt generation source enabled by IRQD, and becomes "0" automatically
during an interrupt transition cycle if an interrupt is accepted.

A bit of IRQ can be set to "1" or "0" by the program.

At reset (when the 

RES

 signal is input, the BRK instruction is executed, the watchdog

timer is overflown, or an operation code trap is generated), IRQ0L, IRQ0H, IRQ1L, and
IRQ1H become 00H, and IRQ2L becomes C0H.

[3]

Interrupt Enable Register IE (IE0L, IE0H, IE1L, IE1H, IE2L)

The IE is a register that specifies an interrupt generation enable/disable independently.
If a bit of IE is "0", the corresponding interrupt generation is disabled. If a bit of IE is "1",
the corresponding interrupt generation is enabled.

At reset (when the 

RES

 signal is input, the BRK instruction is executed, the watchdog

timer is overflown, or an operation code trap is generated), IE0L, IE0H, IE1L, and IE1H
become 00H, and IE2L becomes C0H.

[4]

Master Interrupt Enable Flag (MIE)

The MIE is a 1-bit flag on PSW. MIE specifies enable/disable of all maskable interrupt
generation. If MIE is "0", all maskable interrupt generation is disabled. If MIE is "1", the
generation of all independently enabled interrupts are enabled.

[5]

Master Interrupt Priority Flag (MIPF)

The MIPF is a 1-bit flag assigned to bit 6 of NMICON. MIPF specifies valid/invalid of all
maskable interrupt priorities. If MIPF is "0", priority by IPX0 and IPX1 becomes invalid,
and interrupt generation is controlled only by IE and MIE. If MIPF is "1", four types of
priority, level 0–level 3, are given to all maskable interrupts by IPX0 and IPX1.

Summary of Contents for MSM66591

Page 1: ...MSM66591 ML66592 User s Manual CMOS 16 bit microcontroller FEUL66591 66592 01 Issue Date Mar 4 2002...

Page 2: ...tion set Description of addressing modes MAC66K Assembler Package User s Manual Package overview Description of RAS66K relocatable assembler operation Description of RAS66K assembly language Descripti...

Page 3: ...el of the low side of the voltage indicates voltage level of VIL and VOL described in the electrical characteristics Opcode trap Operation code trap Occurs when an empty area that has not been assigne...

Page 4: ...ut Pins 2 4 2 8 P7_0 P7_7 Input Output Pins 2 5 2 9 P8_0 P8_7 Input Output Pins 2 6 2 10 P9_0 P9_7 Input Output Pins 2 6 2 11 P10_0 P10_7 Input Output Pins 2 7 2 12 P11_0 P11_7 Input Output Pins 2 8 2...

Page 5: ...Memory Access 3 12 1 Byte Operation 3 12 2 Word Operation 3 12 3 2 Registers 3 13 3 2 1 Arithmetic Register ACC 3 13 3 2 2 Control Register 3 14 1 Program Status Word PSW 3 14 2 Program Counter PC 3...

Page 6: ...rdware Configuration of Each Port 6 1 6 1 1 Configuration of Type A P0_0 P0_7 P1_0 P1_7 P12_0 6 4 6 1 2 Configuration of Type B P2_0 P2_7 P3_0 P3_3 P7_4 P7_7 P8_0 P8_7 P10_0 P10_4 6 5 6 1 3 Configurat...

Page 7: ...2 Chapter 11 Flexible Timer FTM 11 1 Configuration of Counter Part 11 6 11 2 Counter Selection Part 11 8 11 3 Type A1 Register Modules TMR0 TMR3 11 10 11 3 1 Configuration of Type A1 Register Modules...

Page 8: ...tput Control Registers RTOCON4 RTOCON13 11 24 11 5 2 Operation of Type B Register Modules TMR4 TMR13 11 26 11 6 Type D Register Module TMR17 11 27 11 6 1 Configuration of Type D Register Module TMR17...

Page 9: ...n of PWM 13 4 1 PWM Counters PWC0 PWC11 13 4 2 PWM Counter Buffer Registers PWC0BF PWC11BF 13 4 3 PWM Registers PWR0 PWR11 13 5 4 PWM Buffer Registers PW0BF PW11BF 13 5 5 Comparison Circuit 13 5 6 Out...

Page 10: ...iguration of Serial Ports 15 2 15 2 Serial Port Control Registers 15 5 15 2 1 Control Registers for SCI0 15 5 1 SCI0 Transmit Control Register ST0CON 15 5 2 SCI0 Receive Control Register SR0CON 15 7 3...

Page 11: ...e Buffer Registers S3BUF1 S3BUF2 S3BUF3 15 44 5 SCI3 Transmit and Receive Registers 15 44 6 SCI3 Status Register 0 S3STAT0 15 45 7 SCI3 Status Register 1 S3STAT1 15 48 8 SCI3 Status Register 2 S3STAT2...

Page 12: ...NTCON1 16 17 7 A D Hard Select Register 0 ADHSEL0 16 19 8 A D Hard Select Register 1 ADHSEL1 16 22 9 A D Hard Select Software Control Register ADHSCON 16 25 10 A D Hard Select Enable Register ADHENCON...

Page 13: ...ty Control Register IPX0 IP00L IP00H IP10L IP10H IP20L IPX1 IP01L IP01H IP11L IP11H IP21L 20 7 20 3 Operation of Maskable Interrupt 20 8 Chapter 21 Bus Port Functions 21 1 Bus Port P0 P1 P12_0 P12_1 F...

Page 14: ...nitor Function Operation 24 5 1 Setting the addresses 24 5 2 Detection of address matching 24 5 3 Reading data 24 5 Chapter 25 Electrical Characteristics MSM66591 Electrical Characteristics 25 1 25 1...

Page 15: ...Contents 12...

Page 16: ...it Timer Function 13 Chapter 13 PWM Functions 14 Chapter 14 Baud Rate Generator Functions 15 Chapter 15 Serial Port Functions 16 Chapter 16 A D Converter Functions 17 Chapter 17 Transition Detector Fu...

Page 17: ......

Page 18: ...Overview Chapter 1 1...

Page 19: ......

Page 20: ...reased by 2K bytes 1A00H to 21FFH Changed from 2000H to 3000H Increased by 64K bytes SEG2 One valid bit has been added to each of CSR and TSR Access forbidden to the internal SEG3 2000H 4000H 8000H 1...

Page 21: ...essing Pointing register indirect addressing Stack addressing Immediate addressing 3 Minimum Instruction Cycle MSM66591 83 3 nsec 12 MHz internal 24 MHz ML66592 71 4 nsec 14 MHz internal 28 MHz 4 Prog...

Page 22: ...ith a 4 stage buffer on the receive side 4 UART synchronous type with BRG 1 Synchronous with 8 byte FIFO 1 12 A D Converter 10 bit resolution 24 channels 12 channel 2 13 Transition Detector 8 14 Watch...

Page 23: ...P6 P5 P4 P3 P2 P1 P0 OE Serial Port Serial Port with FIFO General Timer PWM A D Converter Port Cont RAM 6K bytes 2 Memory Cont Pointing Reg Local Reg SSP LRB PSW PC CSR TSR ALU ALU Cont ACC WDT ROM 1...

Page 24: ...57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 P4_7 TRN...

Page 25: ...L66592 multiply the original oscillation clock by a factor of 2 to generate the master clock pulse CLK One master clock pulse CLK forms one state In other words one state is 41 7 nsec 12 MHz for the M...

Page 26: ...LB A P3 instruction Execution of MOVB off N8 DP instruction DP 0024H LRB internal RAM area Execution of next instruction off N8 DP RAM P4 AL P3 Fetch of 2nd byte of LB A P3 instruction Fetch of MOVB...

Page 27: ...N8 instruction Execution of next instruction P4 N8 P3 AL Fetch of 2nd byte of STB A P3 instruction Fetch of MOVB P4 N8 instruction Fetch of STB A P3 instruction Fetch of 2nd byte of MOVB P4 N8 instruc...

Page 28: ...timing for the RUN bit that becomes 1 differs depending on the instruction executed The timing to read TM1 differs depending on the instruction executed The count timing of TM1 differs depending on t...

Page 29: ...17 cycles if the program memory space is extended to 128K bytes IRQ is reset 0 at the 3rd cycle of the interrupt transition cycle S2 S1 M1S1 Master clock CLK internal State FFFC FFFD FFFE FFFF 0000 0...

Page 30: ...Description of Pins Chapter 2 2...

Page 31: ......

Page 32: ...ns of Port 1 I O can be specified in bit units by the Port 1 mode register P1IO By setting the EA pin to L leve P1_0 P1_7 also function as output pins for internal operations secondary function Descri...

Page 33: ...econdary function control register P3SF For the pins that have secondary functions set by P3SF I O settings by P3IO become invalid Description of Secondary Functions of Each Pin FTM17A P3_0 When regis...

Page 34: ...6 P5_0 P5_7 Input Output Pins 8 bit I O pins of Port 5 I O can be specified in bit units by the Port 5 mode register P5IO P5_0 P5_7 also function as output pins for internal operations secondary funct...

Page 35: ...F For pins that have secondary functions set by P6SF I O settings by P6IO become invalid Description of Secondary Functions of Each Pin INT0 P6_0 INT1 P6_1 Input pins for external interrupts 0 and 1 R...

Page 36: ...obe signal to externally latch the lower 8 bits of the address output from P0 If the EA pin has been set to a L level the pin function automatically changes to the secondary function If both the EA an...

Page 37: ...pin 71 is in L level when P8 is in output status these pins output H or L level but if the OE pin is in H level these pins go into high impedance status 2 10 P9_0 P9_7 Input Output Pins 8 bit I O pin...

Page 38: ...10_7 are set in bit units by the Port 10 secondary function control register P10SF For the pins that have secondary functions set by P10SF I O settings by P10IO be come invalid Description of Secondar...

Page 39: ...bits can be specified as input or output by the Port 11 mode register P11IO P11_0 P11_3 also function secondary and tertiary functions as I O pins for internal operation Description of Secondary Tert...

Page 40: ...7 that is used to access external expanded program memory ML66592 only 2 14 AI0 AI23 Input Pins Analog input pins of the A D converter 2 15 AVDD Input Pin Power input pin of the A D converter Supply t...

Page 41: ...66591 ML66592 mask ROM version 2 23 TEST Input Pin Load test pin Connect to GND In the MSM66Q591 ML66Q592 flash EEPROM version this pin becomes a high voltage supply pin while writing to the flash EEP...

Page 42: ...NT DATA Hiz CONT Type 5 6 IN OUT During output VDD DATA Hiz CONT Type 3 During type 5 input Schmitt inverter input CMOS During type 6 input Schmitt inverter input TTL push pull output that can output...

Page 43: ...Pin Recommended pin handling P0_0 P0_7 P1_0 P1_7 P2_0 P2_7 P3_0 P3_7 P4_0 P4_7 P5_0 P5_5 P6_0 P6_7 P7_0 P7_7 P8_0 P8_7 P9_0 P9_7 P10_0 P10_7 P11_0 P11_7 AI0 AI23 AVDD VREF AGND OE NMI EA For input set...

Page 44: ...CPU Architecture Chapter 3 3...

Page 45: ......

Page 46: ...y model by setting the LROM bit bit 1 to 1 Write 0 to bit 0 To write to the LROM bit of MEMSCON first write 5H to the high order 4 bits low order 4 bits are arbitrary data of the memory size accepter...

Page 47: ...memory in 64K 65536 byte unit seg ment for segments 0 1 and 2 Since segment 3 is not provided do not try to access it However if more than 64K bytes segments 1 and 2 are accessed the LROM bit of the M...

Page 48: ...0076H Vector table area 12 bytes Figure 3 1 a Memory Map of MSM66591 Program Memory Space Figure 3 1 b Memory Map of ML66592 Program Memory Space 17FFH 1800H FFFFH 0FFFH 1000H 0069H 006AH 0049H 004AH...

Page 49: ...tes as a bus port In MSM66591 the internal program fetch enable area is 00000H 1FFFDH This means that the final address of instruction code must not exceed 1FFFDH The final address of the table data i...

Page 50: ...le buffer RTO11 event generation 0028 Interrupt by SCI1 transmit receive 002A Interrupt by S0TM S1TM S2TM S3TM S4TM overflow 002C Interrupt by GTMC GEVC overflow 002E Interrupt by end of conversion by...

Page 51: ...s is significant data and program execution is started from the loaded address If however the program memory space is expanded to 128K bytes MSM66591 or 192K bytes ML66592 the SSP is decremented by 4...

Page 52: ...ory space for each segment 1000H 17FFH is an area that can directly call subroutines by a 2 byte call instruction ACAL Since the ACAL instruction can call subroutines in the current segment when an AC...

Page 53: ...bytes ML66592 53248 bytes The pointing register area PR 64 bytes and the special bit addressing area sbafix 64 bytes are located in the fixed page area In MSM66591 access to the area from 1A00H FFFFH...

Page 54: ...nction registers that the SFR area has are assigned to the 256 byte area of data memory space 0100H 01FFH 3 Internal RAM Area In the MSM66591 internal RAM is assigned to the 6K 6144 byte area of data...

Page 55: ...igned to the 256 byte area of data memory space 0200H 02FFH a pointing register PR area and a special bit address area sbafix The pointing register area is assigned to 0200H 023FH and it has 8 sets of...

Page 56: ...FFFH in the data memory space of the MSM66591 is not allocated as data memory However this area is used by the ROM window function if set by the ROM window setting register The 52K 53248 byte area fro...

Page 57: ...ss in which the least significant bit LSB 0 even address becomes low order 8 bit data and 8 bit data indicated by an address in which LSB 1 odd address becomes high order 8 bit data 16 bit data where...

Page 58: ...Segment register TSR 3 2 1 Arithmetic Register ACC The 16 bit arithmetic register is the accumulator ACC a central register for various operations If the transfer operation etc is Word type all 16 bit...

Page 59: ...specify enable 1 or disable 0 of an entire maskable interrupt MIE flags that the user can freely use F0 2 flags available for future expansion of CPU core functions The user can freely use these flag...

Page 60: ...ero flag is set to 1 if the value is zero as a result of an arithmetic instruction execution the loaded content is zero when a load instruction to ACC is executed the target bit is zero when a bit ope...

Page 61: ...t of executing an arithmetic instruction exceeds the range expressed by a complement of 2 128 to 127 in the case of a byte operation 32768 to 32767 in the case of a word operation otherwise it is set...

Page 62: ...s not change even if an overflow occurs because of an increment in PC At reset when the RES signal is input the BRK instruction is executed the watchdog timer is overflown or an operation code trap is...

Page 63: ...56 byte units The area of addresses 1A00H through 1FFFH is excluded 4 System Stack Pointer SSP SSP is a 16 bit register that indicates the stack address to save or return PC registers etc while handli...

Page 64: ...er USP PR is assigned to 0200H 023FH of the internal RAM area and one of the 8 sets is selected by SCB0 2 of PSWL If the PR function is not used PR can be used as internal RAM For all of X1 X2 DP and...

Page 65: ...the local register base 1 byte of the specified 8 bytes is assigned as R by 3 bit data of a local register operation instruction 2 bytes are assigned as ER by 2 bit data ER0 R0 R1 ER1 R2 R3 ER2 R4 R5...

Page 66: ...t No other methods can reload CSR Since in the MSM66591 CSR has only one valid bit while in the emulator for the MSM66591 CSR has two valid bits specify either segment 0 or segment 1 when executing th...

Page 67: ...the MSM66591 TSR has only one valid bit while on the emulator for the MSM66591 TSR has two valid bits be sure to write 0s to bits 1 to 7 when writing to TSR In ML66592 only bits 0 and 1 of TSR are va...

Page 68: ...R function Abbreviated Abbreviation of name and data address symbol in assembler Name Specifically SSP LRB LRBL LRBH PSW PSWL and PSWH become ASSP ALRB ALRBL ALRBH APSW APSWL and APSWH respectively R...

Page 69: ...eration to a read only SFR B A read operation to a write only SFR C A 16 bit operation to an 8 bit operation only SFR D An 8 bit operation to a 16 bit operation only SFR E A 1 bit operation to a 16 bi...

Page 70: ...5 Data Register Port 4 Data Register Port 3 Data Register Port 2 Data Register Port 1 Data Register Port 0 Data Register S1STAT S1BUF P3SF P2SF P11 P10 P9 P8 P7 P6 P5 P4 P3 P2 P1 P0 SCI0 Receive Buffe...

Page 71: ...er Register 3 Undefined Undefined S3BUF1 SCI3 Receive Buffer Register 3 SCI3 Receive Buffer Register 2 SCI3 Receive Buffer Register 1 PWC0 PWC0BF IE1 IRQ1 IRQ0 IE0 0030 Undefined S4BUF1 SCI4 Receive B...

Page 72: ...r Register PWR3 PW3BF PWM Register 4 PWR4 Buffer Register PWR4 PW4BF PWM Register 5 PWR5 Buffer Register PWR5 PW5BF PWM Register 6 PWR6 Buffer Register PWR6 PW6BF PWM Register 7 PWR7 Buffer Register P...

Page 73: ...gister 10 Timer Register 11 Timer Register 12 Timer Register 13 Timer Register 14 Timer Register 15 Timer Register 16 Timer Register 17 R Address H Name Abbreviated Name BYTE R W 8 16 Bit Operation Re...

Page 74: ...ON12 RTO Control Register 12 F8 RTOCON13 RTO Control Register 13 F8 RTOCON16 RTO Control Register 16 F8 RTOCON17 RTO Control Register 17 00 RTO4CON 4 Port RTO Control Register 0F TM0L Timer Counter 0...

Page 75: ...in the address column marked by indicate that the register has bits missing 00D8 R 00D9 00DA 00DB 00DC 00DD 00DE 00DF Undefined 00E0 00E1 00E2 00E3 00E4 00E5 00E6 00E7 00E8 TMR0L TMR0 Low Order 4 Bit...

Page 76: ...he value of the PWM register PWRn is read When a write operation is performed data is written to the PWR buffer register PWnBF 3 Indicates that the R W operation of ADCR is a special operation ADCR is...

Page 77: ...ol Register R W 8 R W 8 00 P0IO Port 0 Mode Register 00 P1IO Port 1 Mode Register 00 P2IO Port 2 Mode Register 00 P3IO Port 3 Mode Register 00 P4IO Port 4 Mode Register 00 P5IO Port 5 Mode Register 00...

Page 78: ...r 8A ST4CON SCI4 Transmit Control Register 8 12 SR0CON SCI0 Receive Control Register 08 SR1CON SCI1 Receive Control Register 12 SR2CON SCI2 Receive Control Register 12 SR3CON SCI3 Receive Control Regi...

Page 79: ...Register 0000 TRNS Control Register TRNSCON R W 16 C0 EVDV0 Event Dividing Counter 0 C0 EVDV1 Event Dividing Counter 1 C0 EVDV2 Event Dividing Counter 2 C0 EVDV3 Event Dividing Counter 3 C0 EVDV14 Eve...

Page 80: ...I4 Status Register 2 Address H Name Abbreviated Name BYTE R W 8 16 Bit Operation Reset State H Abbreviated Name WORD Addresses in the address column marked by indicate that the register has bits missi...

Page 81: ...bit 7 5 The flash control register area is used exclusively for the MSM66Q591 ML66Q592 Flash EEPROM version product For details refer to the MSM66Q591 Flash Memory User s Manual or ML66Q592 Flash Mem...

Page 82: ...ddressing formats Data in a table segment is read via the window on a data segment opened by a program See Chapter 5 Memory Control Functions 3 3 1 RAM Addressing RAM addressing modes specify addressi...

Page 83: ...e C carry flag Word Type FILL SSP MOV LRB 401H CLR PSW Byte Type CLRB PSWH INCB PSWL Bit Type MB C BITVAR C Pointing Register Addressing Pointing register contents are accessed Pointing registers are...

Page 84: ...LR USP Byte Type DJNZ X1L LOOP DJNZ X2L LOOP DJNZ DPL LOOP DJNZ USPL LOOP JRNZ DP LOOP D Local Register Addressing Local register contents are accessed Local registers are 256 sets of registers every...

Page 85: ...ifier The sfr can be omitted but then SFR page addressing will only be used when the assembler recognizes that an address is in the SFR page Every microcontroller device has its particular SFR symbols...

Page 86: ...FIXED page addressing specifies an offset in the FIXED page 200H 2FFH in data memory with one byte of instruction code Word byte or bit data can be accessed at the specified address The operand is co...

Page 87: ...address The operand is coded with the off addressing specifier The off can be replaced by but this will have a slightly different meaning when bit data in the SBA area is accessed see sbaoff Badr If a...

Page 88: ...t physical segment of data memory address 0 0FFFFH 64K bytes with two bytes of instruction code excluding access inhibit area Word byte or bit data can be accessed at the specified address The operand...

Page 89: ...USP Indirect Addressing with 7 Bit Displacement n7 DP n7 USP E X1 X2 Indirect Addressing with 16 Bit Base D16 X1 D16 X2 F X1 Indirect Addressing with 8 Bit Register Displacement X1 R0 X1 A A DP X1 Ind...

Page 90: ...t specifies an address in the current physical segment address 0 0FFFFH 64K bytes by the contents of a pointing register exclud ing access inhibit area Word byte or bit data can be accessed at the spe...

Page 91: ...ies an address in the current physical segment of data memory address 0 0FFFFH 64K bytes by the contents of a pointing register excluding access inhibit area Word byte or bit data can be accessed at t...

Page 92: ...ntents of a pointing register as a base and adding a 7 bit displacement with sign embedded in instruction code bits 6 0 bit 6 is a signed bit excluding access inhibit area The range 64 to 63 bytes aro...

Page 93: ...ddress in the current physical segment address 0 0FFFFH 64K bytes Word 16 bit calculations are used to generate the address with overflows ignored Therefore the generated address will be 0 0FFFFH Word...

Page 94: ...dressing with 8 bit register displacement specifies an address in the current physical segment address 0 0FFFFH 64K bytes using the contents of a pointing register as a base and adding the contents of...

Page 95: ...A FIXED Page SBA Area Addressing sbafix Badr B Current Page SBA Area Addressing sbaoff Badr A FIXED Page SBA Area Addressing FIXED page SBA area addressing specifies a bit address in the FIXED page s...

Page 96: ...gned expressions For words that range is from 8000H to 0FFFFH and for bytes it is from 80H to 0FFH Word Type L A 1234H MOV X1 WORD_ARRAY_BASE Byte Type LB A 12H MOVB X1 BYTE_ARRAY_BASE 2 Table Data Ad...

Page 97: ...ructions LC LCB CMPC and CMPCB Word Type LC A A CMPC A 1234 X1 Byte Type LCB A ER0 CMPCB A VAR C RAM Addressing Indirect Addressing with 16 Bit Base RAM addressing indirect addressing with 16 bit base...

Page 98: ...sing can be used with J and CAL instructions Example of Use J 3000H CAL LABEL B FAR Code Addressing Far code addressing specifies an address 0 0 1 0FFFFH 128K bytes in program memory space with three...

Page 99: ...ith 4 bits of instruction code The vector table is located at even ad dresses in the range 004AH 0069H in segment 0 This addressing can be used only with VCAL instructions Example of Use VACL 4AH VCAL...

Page 100: ...e data in ROM space using RAM addressing This mode reads data in the table segment specified by TSR using data segment window opened by the program See ROM Window Function Data memory addressing is pe...

Page 101: ...3 56 MSM66591 ML66592User sManual Chapter 3 CPU Architecture...

Page 102: ...CPU Control Functions Chapter 4 4...

Page 103: ......

Page 104: ...ion The MSM66591 ML66592 standby function has two types of operation modes HALT mode stops the clock supply CPU by software STOP mode stops the original oscillation clock supply by software Each mode...

Page 105: ...impedance No change P7_2 P7_3 primary function No change High impedance No change P7_3 secondary function PSEN H level High impedance H level P7_2 secondary function ALE L level High impedance L level...

Page 106: ...hrough current will not flow into the input circuits of pins in high impedance status even if the pin becomes open externally The through current prevention circuit however does not operate for extern...

Page 107: ...by a non maskable interrupt HALT mode is cleared unconditionally and the CPU executes a non maskable interrupt process A maskable interrupt clears HALT mode if both an interrupt request flag IRQ bit a...

Page 108: ...are 1 After STOP mode is cleared the maskable interrupt process is executed if the master interrupt enable flag MIE of PSW is 1 If the master interrupt enable flag MIE of PSW is 0 the instruction nex...

Page 109: ...S pin input apply L level until more than 1 ms has elapsed after the original oscillation clock is stable The reset process has priority over all other processes interrupt process instruction executio...

Page 110: ...0 P7_1 P7_4 P7_7 P8 P11 P12_0 P12_1 Status Hiz Hiz H level pull up Hiz Hiz RES VDD Reset Processing Circuit SW and R are needed for manual reset VDD Di R SW C External Internal Notes 1 If the EA pin i...

Page 111: ...4 8 MSM66591 ML66592User sManual Chapter 4 CPU Control Functions...

Page 112: ...Memory Control Functions Chapter 5 5...

Page 113: ......

Page 114: ...at the same address in the segment in the program memory space specified by TSR is accessed read To the instruction execution cycle 3 cycles are added by one access reading in the case of a byte inst...

Page 115: ...d the ROM window function is disabled ROMWIN can be written only once after reset A second or later writing is ignored This means that once a ROM window function is set it cannot be changed until rese...

Page 116: ...rder 6 bits Figure 5 2 shows the configuration of ROMRDY At reset when the RES signal is input the BRK instruction is executed the watchdog timer is overflown or an operation code trap is generated bo...

Page 117: ...5 4 MSM66591 ML66592User sManual Chapter 5 Memory Control Functions...

Page 118: ...Port Functions Chapter 6 6...

Page 119: ......

Page 120: ...n Type A Has secondary functions as an address data bus and automatically switches to its secondary function when the external memory is accessed Goes into high impedance status if the output status o...

Page 121: ...erial 1 transmission TXC1 I O P6_6 C 1 I O Serial port 0 data input RXD0 Input P6_7 C 1 I O Serial port 0 data output TXD0 Output Port 7 P7_0 P7_1 D 2 I O None P5_7 C 1 I O Wait signal input pin WAIT...

Page 122: ...no P10_6 C 1 I O Expansion port data I O SFTDAT I O no P10_7 C 1 I O Latch strobe output for expansion port SFTSTB Output no Port 11 P11_0 C 1 I O Address input for RAM monitor function RMRX Input no...

Page 123: ...output pins and data I O pins for external program memory access The pin specified as the output goes into high impedance if OE is in H level In the ML66592 P12_1 also is a Type A port Figure 6 1 sho...

Page 124: ...ports act as secondary function input and output pins according to the specification of the secondary function control register PmSFn The pin specified as the output goes into high impedance if OE is...

Page 125: ...L level Then when external program memory is accessed P7_3 func tions as an output pin PSEN pin for a strobe signal to be output for a read operation and P7_2 functions as an output pin ALE pin for a...

Page 126: ...ype D ports Figure 6 5 Configuration of Type E 6 1 5 Configuration of Type E P12_1 Type E ports function as I O pins without secondary functions When the OE pin is in H level the pin specified as the...

Page 127: ...by the bit symbol corresponding to each bit Bit symbols for bits of a port data register are for example P0_0 for bit 0 and P0_1 for bit 1 in Port 0 So a port data register is represented correspendin...

Page 128: ...n the RES signal is input the BRK instruction is executed the watchdog timer is overflown or an operation code trap is generated If each bit of PnSF is set to 0 primary function is selected and if 1 s...

Page 129: ...ster 0020 P6SF 00 Port 7 Secondary Function Control Register P7SF 00 Port 8 Secondary Function Control Register 0022 P8SF 00 Port 9 Secondary Function Control Register 0023 P9SF 00 Port 10 Secondary F...

Page 130: ...ation code trap is generated Port 0 goes into high impedance input port P0IO 00H The content of P0 becomes 00H P0_7 P0_6 P0_5 P0_4 P0_3 P0_2 P0_1 P0_0 7 6 5 4 3 2 1 0 P0 P0IO7 P0IO6 P0IO5 P0IO4 P0IO3...

Page 131: ...IO If a read instruction is executed to P1 in which input is specified P1IOn 0 by P1IO the content of the pin is read If a read instruction is executed to P1 in which output is specified P1IOn 0 the c...

Page 132: ...gure 6 8 shows the configuration of the Port 2 data register P2 the Port 2 mode register P2IO and the Port 2 secondary function control register P2SF P2_7 P2_6 P2_5 P2_4 P2_3 P2_2 P2_1 P2_0 7 6 5 4 3...

Page 133: ...ed to P2 the content of the pin or port data register is read according to specification by P2IO when reading and data is written to the port data register when writing At reset when the RES signal is...

Page 134: ...register P3IO and the Port 3 secondary function control register P3SF Figure 6 9 Configuration of P3 P3IO and P3SF P3_7 P3_6 P3_5 P3_4 P3_3 P3_2 P3_1 P3_0 7 6 5 4 3 2 1 0 P3 P3IO7 P3IO6 P3IO5 P3IO4 P...

Page 135: ...ding to specification by P3IO when reading and data is written to the port data register when writing At reset when the RES signal is input the BRK instruction is executed the watchdog timer is overfl...

Page 136: ...4 the Port 4 mode register P4IO and the Port 4 secondary function control register P4SF Figure 6 10 Configuration of P4 P4IO and P4SF P4_7 P4_6 P4_5 P4_4 P4_3 P4_2 P4_1 P4_0 7 6 5 4 3 2 1 0 P4 P4IO7 P...

Page 137: ...ecuted to Port 4 the content of the pin or port data register is read according to specification by P4IO when reading and data is written to the port data register when writing At reset when the RES s...

Page 138: ...P5_2 P5_1 P5_0 7 6 5 4 3 2 1 0 P5 P5IO7 P5IO6 P5IO5 P5IO4 P5IO3 P5IO2 P5IO1 P5IO0 7 6 5 4 3 2 1 0 P5IO P5_n input 0 P5_n output 1 n 0 7 6 8 Port 5 P5 Port 5 P5_0 P5_7 is a 8 bit I O port Input or out...

Page 139: ...arithmetic instruction increment instruction or instruction of that type read modify write instruction is executed to P5 the content of the pin or port data register is read according to specification...

Page 140: ...gister P6IO and the Port 6 secondary function control register P6SF Figure 6 12 Configuration of P6 P6IO and P6SF P6_7 P6_6 P6_5 P6_4 P6_3 P6_2 P6_1 P6_0 7 6 5 4 3 2 1 0 P6 P6IO7 P6IO6 P6IO5 P6IO4 P6I...

Page 141: ...to P6 according to the content of P6I0 and P6SF If an arithmetic instruction increment instruction or instruction of that type read modify write instruction is executed to Port 6 the content of the p...

Page 142: ...8 bit I O port Input or output can be specified for each bit by the Port 7 mode register P7IO In addition to the port function a secondary function output of the strobe signal for the external memory...

Page 143: ...port data register is read according to specification by P7IO when reading and data is written to the port data register when writing At reset when the RES signal is input the BRK instruction is exec...

Page 144: ...l But if the OE pin pin 71 is in H level Port 8 goes into high impedance status Figure 6 14 shows the configuration of the Port 8 data register P8 the Port 8 mode register P8IO and the Port 8 secondar...

Page 145: ...ed to P8 the content of the pin or port data register is read according to specification by P8IO when reading and data is written to the port data register when writing At reset when the RES signal is...

Page 146: ...secondary function control register P9SF Figure 6 15 Configuration of P9 P9IO and P9SF P9_7 P9_6 P9_5 P9_4 P9_3 P9_2 P9_1 P9_0 7 6 5 4 3 2 1 0 P9 P9IO7 P9IO6 P9IO5 P9IO4 P9IO3 P9IO2 P9IO1 P9IO0 7 6 5...

Page 147: ...arithmetic instruction increment instruction or instruction of that type read modify write instruction is executed to P9 the content of the pin or port data register is read according to specificatio...

Page 148: ...igh impedance status Figure 6 16 shows the configuration of the Port 10 data register P10 the Port 10 mode register P10IO and the Port 10 secondary function control register P10SF Figure 6 16 Configur...

Page 149: ...e port data register when writing At reset when the RES signal is input the BRK instruction is executed the watchdog timer is overflown or an operation code trap is generated Port 10 becomes a high im...

Page 150: ...0 P11_n output 1 n 0 7 Figure 6 17 Configuration of P11 and P11IO If a read instruction is executed to P11 in which the input is specified P11IOn 0 by P11IO the content of the pin is read If a read in...

Page 151: ...2 mode register P12IO Figure 6 18 Configuration of P12 and P12IO If a read instruction is executed to P12 in which input is specified P12IOn 0 by P12IO the content of the pin is read If a read instruc...

Page 152: ...Output Pin Control Pin OE Chapter 7 7...

Page 153: ......

Page 154: ...P2 P3_0 P3_3 P7_4 P7_7 P8 P10_0 P10_4 P12_0 and P12_1 are configured to function as output pins each pin goes into high impedance status and if the OE pin is in L level each pin outputs L or H level W...

Page 155: ...7 2 MSM66591 ML66592User sManual Chapter 7 Output Pin Control Pin OE...

Page 156: ...Clock Generation Circuit Chapter 8 8...

Page 157: ......

Page 158: ...nnection example for external clock input Figure 8 1 An Example of a Crystal Oscillation Circuit Connection Figure 8 2 Connection Example for External Clock Input Oscillation Circuit Clock pulse contr...

Page 159: ...ed by an interrupt request the master clock pulse is transferred when the number of clocks specified by OST0 and OST1 bits 4 and 5 of SBYCON have elapsed after oscillation starts If STOP mode is clear...

Page 160: ...Time Base Counter TBC Chapter 9 9...

Page 161: ......

Page 162: ...peration code trap is gener ated and from then on operates unless the supply of the original oscillation clock stops Figure 9 1 shows the configuration of TBC Figure 9 1 Configuration of TBC 1 CLK in...

Page 163: ...F0H TBCKDVR TBCKDVR is a 4 bit register that stores reload values into TBCKDVC Write is valid but write to high order 4 bits is invalid Read is valid but the high order 4 bits will read 1 if read At...

Page 164: ...Watchdog Timer WDT Chapter 10 10...

Page 165: ......

Page 166: ...or 1 512 TBCCLK Figure 10 1 Configuration of WDTCON 10 2 Operation of WDT 1 256 TBCCLK or 1 512 TBCCLK can be selected for the WDT input clock by the WDTSEL bit bit 0 of the WDT control register WDTC...

Page 167: ...tWDT 1 f sec n 28 occurs since the content of TBC does not change When the master clock of the MSM66591 is 24 MHz and n 8 the result is tWDT 43 69 msec tWDT 85 33 sec When the master clock of the ML66...

Page 168: ...Content of WDT 3CH write WDT start C3H write WDT clear to 0 3CH write WDT clear to 0 C3H write WDT clear to 0 within tWDT within tWDT within tWDT a When program is executed normally Content of WDT 3CH...

Page 169: ...o writing to WDT Progress of program during an abnormal execution Progress of program during a normal execution WDT is cleared to 0 by writing 3CH to WDT WDT is cleared to 0 by writing C3H to WDT WDT...

Page 170: ...Flexible Timer FTM Chapter 11 11 11...

Page 171: ......

Page 172: ...fourteen 16 bit registers control registers and other components The functions of the timer include 20 bit capture modes 4 type A1 16 bit capture modes 2 type A2 double buffer real time output modes 1...

Page 173: ...TM0 20 bit TM1 16 bit TMCON 8 bit Counter Selection Part TMSEL 16 bit TMSEL2 8 bit Type A1 Register Modules TMR0 TMR3 TMRL0 TMRL3 CAPCON EVDV0 EVDV3 EVDV0BF EVDV3BF EVNTCONL EVNTCONH Type A2 Register...

Page 174: ...5 Timer Register 6 Timer Register 7 Timer Register 8 Timer Register 9 Timer Register 10 Timer Register 11 Timer Register 12 Timer Register 13 Timer Register 14 Timer Register 15 Timer Register 16 Time...

Page 175: ...ol Register 13 RTO Control Register 16 Timer Counter 0 Timer Counter 1 TMR0 Low order 4 Bits TMR1 Low order 4 Bits TMR2 Low order 4 Bits TMR3 Low order 4 Bits TMSEL2 RTOCON4 RTOCON5 RTOCON6 RTOCON7 RT...

Page 176: ...EVDV15 C0 EVDV0BF C0 EVDV1BF C0 EVDV3BF C0 EVDV14BF C0 EVDV15BF C0 8 R W Event Dividing Counter 14 EVDV2 Buffer Register EVDV15 Buffer Register EVDV2BF EVDV14 C0 C0 017C 017D 017E CAPCON Capture Contr...

Page 177: ...mer 0 is a 20 bit counter the low order 4 bits are TM0L and the high order 16 bits are TM0 and can be read written by the program However if TM0 is read the con tents of TM0L are latched to the tempor...

Page 178: ...16 TBCCLK 1 0 1 1 32 TBCCLK 1 1 0 1 64 TBCCLK 1 1 1 1 128 TBCCLK TM1RUN TM1CK2 TM1CK1 TM1CK0 TM0RUN TM0CK2 TM0CK1 TM0CK0 7 6 5 4 3 2 1 0 TMCON Figure 11 3 Configuration of TMCON TM0 TM1 TM0 TM1 TM0 TM...

Page 179: ...gister 0 TMR0 through timer register 3 TMR3 consist of 20 bits TM0L4 is always connected to the low order 4 bits regardless of the specifica tion of TMSEL 1s are read from bits 7 2 when TMSEL2 is read...

Page 180: ...TMSEL Figure 11 6 Configuration of TMSEL2 15 14 13 12 11 10 9 8 0 TMR8 is connected to TM0 1 TMR8 is connected to TM1 0 TMR9 is connected to TM0 1 TMR9 is connected to TM1 0 TMR10 is connected to TM0...

Page 181: ...nction control register to 1 Figure 17 1 shows the configuration of type A1 register module Figure 11 7 Configuration of Type A1 Register Module 1 Timer Registers TMR0 TMR0L TMR3 TMR3L The timer regis...

Page 182: ...CAP3 P3_7 pins Since CAPCON has only 16 bit access bit manipulation instructions such as SB and RB cannot be used At reset when the RES signal is input the BRK instruction is executed the watchdog tim...

Page 183: ...d a 1 1 division is specified Figure 11 9 shows the configuration of EVNTCONL and Figure 11 10 the configuration of EVNTCONH T1EV2 T1EV1 T1EV0 T0EV2 T0EV1 T0EV0 T0EV Dividing ratio of valid edge of CA...

Page 184: ...8 division 1 0 0 1 16 division 1 0 1 1 32 division 1 1 1 64 division 7 6 5 4 3 2 1 0 T3EV Dividing ratio of valid edge of CAP3 pin 2 1 0 0 0 0 1 1 division 0 0 1 1 2 division 0 1 0 1 4 division 0 1 1...

Page 185: ...Registers EVDV0BF EVDV3BF EVDV0BF EVDV3BF are 6 bit registers that hold the content of EVDV0 EVDV3 content just prior to being cleared to 0 when a capture event is generated Figure 11 12 shows the co...

Page 186: ...only once even if the capture event is input twice or more at an interval of less than 3 CLKs Figure 11 13 a and b shows capture operation timing examples Figure 11 13 a Capture Operation Timing Examp...

Page 187: ...pture pin EVDVn counts their number If the counter value and the dividing value specified by EVNTCONL or EVNTCONH match a capture event is generated If a capture event is generated a capture interrupt...

Page 188: ...used as a capture function set the bit corresponding to the Port 10 secondary function control register to 1 Figure 11 14 shows the configuration of a type A2 register module Figure 11 14 Configuratio...

Page 189: ...ot be used At reset when the RES signal is input the BRK instruction is executed the watchdog timer is overflown or an operation code trap is generated CAPCON becomes 0000H and CAP0 CAP3 CAP14 CAP15 F...

Page 190: ...88H and a 1 1 division is specified Figure 11 16 shows the configuration of EVNTCON2 Figure 11 16 Configuration of EVNTCON2 T15EV2 T15EV1 T15EV0 T14EV2 T14EV1 T14EV0 T14EV Dividing ratio of valid edg...

Page 191: ...EVDV14 and EVDV15 become C0H 5 EVDV14 EVDV15 Buffer Registers EVDV14BF EVDV15BF EVDV14BF and EVDV15BF are 6 bit registers that hold the content of EVDV14 and EVDV15 content just prior to being cleared...

Page 192: ...ed Interrupt request is generated 11 4 2 Operation of Type A2 Register Modules TMR14 TMR15 If the valid edge specified by CAPCON is input to CAP14 or CAP15 pin when the TM specified by TMSEL is in RUN...

Page 193: ...g value specified by EVNTCON2 match a capture event is generated If a capture event is generated a capture interrupt request is generated the counter value is loaded to the timer register the EVDVn va...

Page 194: ...egisters TMR4 TMR13 TMR4BF TMR13BF pins to output signals by the real time output function RTO4 RTO13 a timing controller a comparator to compare timer counter and timer register values and control re...

Page 195: ...e watchdog timer is overflown or an operation code trap is generated TMR4BF TMR13BF become 0000H 3 Real time Output Control Registers RTOCON4 RTOCON13 A real time output control register RTOCON4 RTOCO...

Page 196: ...The content of this flag is output to an RTOn pin If the selected counter value and the TMRn value match the content of this flag is loaded to TnOUT If the selected counter value and the TMRn value ma...

Page 197: ...erefore set the time for the next event to TMR4 TMR13 and set the time for the event after the next event to TMR4BF TMR13BF Set the state for the next event to TnBF0 and set the state for the event af...

Page 198: ...FTM17A FTM17D to either input capture signals or output signals by the real time output function a timing controller a comparison circuit to compare timer counter and timer register values a control...

Page 199: ...M TMD T17BF0 FTM17B Timing Controller 17 CLK T17SEL TMDS Comparison Circuit TMR17 T17OUT Interrupt request T17CER TMD CAP17 T17BFA T17OUTA T17BFB T17OUTB T17BFD T17OUTD T17BFC T17OUTC FTM17C FTM17D CA...

Page 200: ...the state for the next event to TnBF0 4 port real time output register RTO4CON consists of 8 bits When TMR17 is in 4 port RTO mode if TMR17 matches the counter value specified by TMSEL2 the content o...

Page 201: ...lag is loaded to T17OUT When TMR17 is in CAP mode if the selected counter completes one cycle during a capture event the content of this flag is 1 if not 0 indicates a bit that is not provided 1 is re...

Page 202: ...the watchdog timer is overflown or an operation code trap is generated TMRMODE becomes F2H TMR16 is specified to RTO mode and TMR17 is specified to 4 port output RTO mode Figure 11 26 shows the confi...

Page 203: ...use CAPCON has only 16 bit access At reset when the RES signal is input the BRK instruction is executed the watchdog timer is overflown or an operation code trap is generated CAPCON becomes 0000H and...

Page 204: ...0 Therefore set to TMR17 the time for the next event and set to T17BF0 the state for the next event The RTO4CON function becomes invalid Figure 11 28 shows an example of a type D register module opera...

Page 205: ...TMR17 T17BFA T17BFD Interrupt request is generated Write to TMR17 T17BFA T17BFD 2 Operation in 4 Port Output Real time Output Mode 4 Port RTO When the TM specified by TMSEL2 is in RUN status TMR17 is...

Page 206: ...remains at 0 if the cycle is not completed when the capture value is less than or equal to the last capture value The cycle flag is set to 1 at the timing of the next capture operation after the abov...

Page 207: ...timing controller a comparison circuit to compare timer counter and timer register values a control register TMRMODE to specify the operation of a type E register module and control registers RTOCON1...

Page 208: ...0 RTOCON16 can be read written by the program Write is valid however write to high order 5 bits is invalid Read is valid however 1 is always read from the high order 5 bits If a read modify write inst...

Page 209: ...atchdog timer is overflown or an operation code trap is generated TMRMODE becomes F2H TMR16 is specified to RTO mode and TMR17 is specified to 4 port output RTO mode Figure 11 33 shows the configurati...

Page 210: ...e used because CAPCON has only 16 bit access At reset when the RES signal is input the BRK instruction is executed the watchdog timer is overflown or an operation code trap is generated CAPCON becomes...

Page 211: ...odule type D See Figure 11 28 If FTM16 pin is used for RTO functions set the corresponding bit of the Port 10 second ary function control register to 1 2 Operation in CAP Mode When the TM specified by...

Page 212: ...signal of TM1 and TMRn becomes H level while the content of TM1 is 100H TMRn and the RTO output pin change at the fall of the match signal and by the AND signal of the TM1 clock pulse The correspondi...

Page 213: ...11 42 MSM66591 ML66592User sManual Chapter 11 Flexible Timer FTM...

Page 214: ...General Purpose 8 Bit Timer Function Chapter 12 12...

Page 215: ......

Page 216: ...GTM Control SFRs Address H Name Abbreviated Name BYTE R W 8 16 Bit Operation 8 Reset State H 016A General Purpose 8 Bit Timer Control Register GTMCON 30 016B General Purpose 8 Bit Event Counter GEVC 0...

Page 217: ...k P9_6 ETMCK pin at that time 12 1 General Purpose 8 Bit Timer GTM The general purpose 8 bit timer consists of an 8 bit timer counter GTMC an 8 bit timer register GTMR that stores the reload values of...

Page 218: ...er and its content is loaded to GTMC when a GTMC overflow occurs At reset when the RES signal is input the BRK instruction is executed the watchdog timer is overflown or an operation code trap is gene...

Page 219: ...1 4 TBCCLK 0 1 0 1 8 TBCCLK 0 1 1 1 16 TBCCLK 1 0 0 1 64 TBCCLK 1 0 1 1 256 TBCCLK 1 1 0 External rise P9_6 ETMCK pin 1 1 1 External fall P9_6 ETMCK pin 0 GTMC count operation stop 1 GTMC count runs 0...

Page 220: ...mer GTMC When this bit is 0 no interrupt request has been generated When 1 an interrupt request has been generated EEVC bit 2 EEVC enables or disables the generation of interrupt requests by the gener...

Page 221: ...GEVC The GEVC is an 8 bit counter that generates an interrupt request when an overflow occurs The count clock of the GEVC is selected by the high order 2 bits of the general purpose 8 bit timer contro...

Page 222: ...e generation of interrupt requests by the gen eral purpose 8 bit timer GTMC When this bit is 0 interrupts are disabled When 1 interrupts are enabled QGTM bit 1 QGTM indicates whether an interrupt requ...

Page 223: ...12 8 MSM66591 ML66592User sManual Chapter 12 General Purpose 8 Bit Timer Function...

Page 224: ...PWM Functions Chapter 13 13...

Page 225: ......

Page 226: ...a 10 6 msec valid bit length 8 bits to 838 9 msec valid bit length 16 bits cycle can be selected by combining the input clock of the PWM counter and a valid bit length Figure 13 1 shows the configura...

Page 227: ...R3 Buffer Register PWM Register 4 PWR4 Buffer Register PWM Register 5 PWR5 Buffer Register 0052 PWM Register 6 PWR6 Buffer Register PWM Register 7 PWR7 Buffer Register PWM Register 8 PWR8 Buffer Regis...

Page 228: ...ister 2 PWM Control Register 4 0082 PWRUNL PWINTQ0L PWINTQ1L PWINTE0L PWINTE1L PWCON0 PWCON2 PWCON4 PWRUN PWINTQ0 PWINTQ1 PWINTE0 PWINTE1 PWM Control Register 1 PWM Control Register 3 PWM Control Regi...

Page 229: ...er generates an interrupt request PWC0 and PWC1 PWC2 and PWC3 PWC4 and PWC5 PWC6 and PWC7 PWC8 and PWC9 PWC10 and PWC11 are common and the contents of the 16 bit PWM counter buffer register are loaded...

Page 230: ...y compares the content of PWC0 PWC11 and that of PWR0 PWR11 when the corresponding PWnRUN bit is 1 It generates an interrupt request PWM0 and PWM1 PWM2 and PWM3 PWM4 and PWM5 PWM6 and PWM7 PWM8 and PW...

Page 231: ...TBCCLK 0 1 2 TBCCLK 1 1 4 TBCCLK 0 1 8 TBCCLK 1 1 16 TBCCLK 1 0 0 1 1 2 0 0 0 0 1 1 PWM1 high active status PWM1 low active status 0 1 PWCON0 indicates either 1 or 0 PW3ACTPW3CK2PW3CK1PW3CK0PW2ACTPW2C...

Page 232: ...CCLK 1 1 4 TBCCLK 0 1 8 TBCCLK 1 0 0 1 1 2 0 0 0 0 1 PWM5 high active status PWM5 low active status 0 1 PWCON2 1 1 16 TBCCLK 1 1 1 16 TBCCLK 1 indicates either 1 or 0 PW7ACTPW7CK2PW7CK1PW7CK0PW6ACTPW6...

Page 233: ...4 TBCCLK 0 1 8 TBCCLK 1 0 0 1 1 2 0 0 0 0 1 PWM9 high active status PWM9 low active status 0 1 PWCON4 1 1 16 TBCCLK 1 1 1 16 TBCCLK 1 indicates either 1 or 0 PW11ACTPW11CK2PW11CK1PW11CK0PW10ACTPW10CK2...

Page 234: ...RUNH become 00H and F0H respectively and PWC0 PWC11 stop the count operation Figure 13 8 Configuration of PWRUNL PW7RUNPW6RUNPW5RUNPW4RUNPW3RUNPW2RUNPW1RUNPW0RUN 7 6 5 4 3 2 1 0 0 PWC0 stops 1 PWC0 ru...

Page 235: ...1 are flags individual interrupt request flags that are set to 1 if the contents of PWC0 PWC11 and PWR0 PWR11 match The bits of PWINTQ0 and PWINTQ1 do not become 0 automatically even if a correspondin...

Page 236: ...s 0 PWC6 underflow generation no 1 PWC6 underflow generation yes 0 1 0 PWC4 underflow generation no 1 PWC4 underflow generation yes 0 PWC5 underflow generation no 1 PWC5 underflow generation yes PWC7...

Page 237: ...o 1 Match of PWC6 and PWR6 yes 0 1 0 Match of PWC4 and PWR4 no 1 Match of PWC4 and PWR4 yes 0 Match of PWC5 and PWR5 no 1 Match of PWC5 and PWR5 yes Match of PWC7 and PWR7 no Match of PWC7 and PWR7 ye...

Page 238: ...undferflow generation PWINTE1 is a register that controls enable disable of the interrupt request by matching of the contents of PWC0 PWC11 and PWR0 PWR11 Figure 13 14 shows the configuration of PWIN...

Page 239: ...request by PWC6 underflow enabled 0 1 0 Interrupt request by PWC4 underflow disabled 1 Interrupt request by PWC4 underflow enabled 0 Interrupt request by PWC5 underflow disabled 1 Interrupt request by...

Page 240: ...est by match of PWC4 and PWR4 disabled 1 Interrupt request by match of PWC4 and PWR4 enabled 0 Interrupt request by match of PWC5 and PWR5 disabled 1 Interrupt request by match of PWC5 and PWR5 enable...

Page 241: ...f the contents of PWC0 PWC11 and PWR0 PWR11 occur concurrently when PWR 0000H is set the interrupt request by an underflow of PWC0 PWC11 is given priority Therefore only the individual interrupt reque...

Page 242: ...k of PWM TBCCLK dividing ratio of the 1 n counter 1 4 PWCnBF value 00FFH f PWM 24 000 000 1 4 1 255 1 93 750 Hz 10 67 sec Figure 13 18 shows an example of PWM output operation Figure 13 19 shows an ex...

Page 243: ...Chapter 13 PWM Functions Figure 13 19 PWM Output Timing Change Example 100H 0FFH 0FEH PWC clock TBCCLK dividing ratio of the 1 n counter 1 4 Master clock CLK Content of PWC Match signal of PWC and PWR...

Page 244: ...Baud Rate Generator Functions Chapter 14 14...

Page 245: ......

Page 246: ...me except for the address of registers located in the SFR area Interrupts for S0TM S1TM S2TM S3TM and S4TM are assigned to the same interrupt vector The generation of individual interrupt requests are...

Page 247: ...er SCI4 Timer SCI0 Timer Control Register SCI1 Timer Control Register SCI2 Timer Control Register SCI3 Timer Control Register SCI4 Timer Control Register S0CON S1CON S2CON S3CON S4CON S1TM S2TM S3TM S...

Page 248: ...K instruction is executed the watchdog timer is overflown or an operation code trap is generated S0TM becomes 0000H and the count operation stops 3 SCI0 Timer Control Register S0CON S0CON is an 8 bit...

Page 249: ...mode 1 S0TM baud rate generator mode for SCI0 0 SCI0 timer counter overflow generation no 1 SCI0 timer counter overflow generation yes 0 SCI0 timer counter count operation STOP 1 SCI0 timer counter co...

Page 250: ...flow is generated The calculation of the baud rate when SCI0 is used as the baud rate generator is shown below B baud rate f BRG S0TM count clock frequency Hz D reload value 0 to 255 Even if the reloa...

Page 251: ...nstruction is executed the watchdog timer is overflown or an operation code trap is generated S1TM becomes 0000H and the count operation stops 3 SCI1 Timer Control Register S1CON S1CON is an 8 bit reg...

Page 252: ...r mode 1 S1TM baud rate generator mode for SCI1 0 SCI1 timer counter overflow generation no 1 SCI1 timer counter overflow generation yes 0 SCI1 timer counter count operation STOP 1 SCI1 timer counter...

Page 253: ...ud rate generator is shown below UART mode B baud rate f BRG S1TM count clock frequency Hz D reload value 0 to 255 Synchronous mode B baud rate f BRG S1TM count clock frequency Hz D reload value 0 to...

Page 254: ...uction is executed the watchdog timer is overflown or an operation code trap is generated S2TM becomes 0000H and the count operation stops 3 SCI2 Timer Control Register S2CON S2CON is an 8 bit registe...

Page 255: ...mode 1 S2TM baud rate generator mode for SCI2 0 SCI2 timer counter overflow generation no 1 SCI2 timer counter overflow generation yes 0 SCI2 timer counter count operation STOP 1 SCI2 timer counter c...

Page 256: ...ow is generated The calculation of the baud rate when SCI2 is used as the baud rate generator is shown below B baud rate f BRG S2TM count clock frequency Hz D reload value 0 to 255 Even if the reload...

Page 257: ...ction is executed the watchdog timer is overflown or an operation code trap is generated S3TM becomes 0000H and the count operation stops 3 SCI3 Timer Control Register S3CON S3CON is an 8 bit register...

Page 258: ...r mode 1 S3TM baud rate generator mode for SCI3 0 SCI3 timer counter overflow generation no 1 SCI3 timer counter overflow generation yes 0 SCI3 timer counter count operation STOP 1 SCI3 timer counter...

Page 259: ...is generated The calculation of the baud rate when SCI3 is used as the baud rate generator is shown below B baud rate f BRG S3TM count clock frequency Hz D reload value 0 to 255 Even if the reload va...

Page 260: ...ruction is executed the watchdog timer is overflown or an operation code trap is generated S4TM becomes 0000H and the count operation stops 3 SCI4 Timer Control Register S4CON S4CON is an 8 bit regist...

Page 261: ...mode 1 S4TM baud rate generator mode for SCI4 0 SCI4 timer counter overflow generation no 1 SCI4 timer counter overflow generation yes 0 SCI4 timer counter count operation STOP 1 SCI4 timer counter c...

Page 262: ...ow is generated The calculation of the baud rate when SCI4 is used as the baud rate generator is shown below B baud rate f BRG S4TM count clock frequency Hz D reload value 0 to 255 Even if the reload...

Page 263: ...14 18 MSM66591 ML66592User sManual Chapter 14 Baud Rate Generator Functions...

Page 264: ...Serial Port Functions Chapter 15 15...

Page 265: ......

Page 266: ...de and a 4 stage buffer mode Single buffer mode has a single stage of receive buffer and 4 stage buffer mode has four stages of receive buffers ring buffer type Synchronous mode has a master mode to g...

Page 267: ...isters S0STATm S1STAT S2STATm S3STATm S4STATm m 0 2 a transmit register and a receive register Figure 15 1 shows the configuration of SCI0 SCI2 SCI3 and SCI4 Figure 15 2 shows the configuration of SCI...

Page 268: ...1 S4BUF1 Undefined 0036 SCI4 Receive Buffer Register 2 S4BUF2 Undefined 0037 SCI4 Receive Buffer Register 3 S4BUF3 Undefined 0038 SCI0 Status Register 0 S0STAT0 00 0039 SCI0 Interrupt Control Registe...

Page 269: ...T1 11 0193 SCI2 Status Register 2 S3STAT2 C1 0194 SCI3 Status Register 1 S4STAT1 0195 SCI3 Status Register 2 S4STAT2 0196 SCI4 Status Register 1 0197 SCI4 Status Register 2 11 C1 11 C1 S0STAT1 S0STAT2...

Page 270: ...not provided for the transmit side Figure 15 3 shows the configuration of ST0CON Description of Each Bit ST0MD bit 0 This bit specifies the transmit operation mode of SCI0 ST0MPC bit 2 If SCI0 transmi...

Page 271: ...7 6 5 4 3 2 1 0 indicates a bit that is not provided 1 is read if a read instruction is executed 0 SCI0 UART normal mode 1 SCI0 UART multiprocessor communication mode 0 Data transmitted 1 Address tra...

Page 272: ...ves in UART multiprocessor communication mode this bit specifies which is received data or an address The receive data length is 8 bits If this bit is 0 data is received and if 1 an address is receive...

Page 273: ...at is not provided 1 is read if a read instruction is executed 0 SCI0 UART normal mode 1 SCI0 UART multiprocessor communication mode 0 Data is received 1 Address is received 0 1 0 1 0 1 Multiprocessor...

Page 274: ...e buffer mode These registers are read only and cannot be written to During the 4 stage buffer mode at the completion of each 1 byte reception the contents of the receive register are transferred to a...

Page 275: ...ts of S0STAT0 by the program when a receive ends The contents of S0BUF0 must be read before resetting OERR00 bit 1 of the low order 4 bits of S0STAT0 Otherwise the OERR00 flag is set to 1 again irresp...

Page 276: ...I0 UART multi processor communication mode This means that if the MPC bit of the data that is transferred when the SR0MPC bit of SR0CON is 0 is 1 MERR00 is set inter preting this as a multiprocessor c...

Page 277: ...0 parity error yes 0 S0BUF0 multiprocessor communication error no 1 S0BUF0 multiprocessor communication error yes 0 S0BUF0 receive ready interrupt request generation disabled 1 S0BUF0 receive ready in...

Page 278: ...set when the RES signal is input the BRK instruction is executed the watchdog timer is overflown or an operation code trap is generated S0STAT1 becomes 11H Figure 15 6 shows the configuration of S0STA...

Page 279: ...it of SR0CON is 0 is 1 MERR02 is set to 1 interpreting this as a multiprocessor communication error Figure 15 6 Configuration of S0STAT1 7 MERR02 6 PERR02 5 OERR02 4 3 MERR01 2 PERR01 1 OERR01 0 0 1 S...

Page 280: ...ive buffer into which data will be transferred S0BUF0 S0BUF1 S0BUF2 S0BUF3 can be verified by reading bits 4 and 5 of S0STAT2 At reset when the RES signal is input the BRK instruction is executed the...

Page 281: ...yes 0 1 0 1 S0BUF3 multiprocessor communication error no S0BUF3 multiprocessor communication error yes S0BUF3 parity error no S0BUF3 parity error yes BFCU0 1 Buffer counter monitor during SCI0 4 stag...

Page 282: ...abled and if 0 generation is disabled RV0IE2 bit 2 This bit enables or disables the generation of SCI0 S0BUF2 receive ready interrupt requests If this bit is 1 generation is enabled and if 0 generatio...

Page 283: ...enabled 0 1 S0BUF3 receive ready interrupt request generation disabled S0BUF3 receive ready interrupt request generation enabled 0 1 S0BUF0 receive ready generation no see note S0BUF0 receive ready g...

Page 284: ...synchronous multiprocessor communication mode bit 2 ST1MPC specifies which is transmitted data or an address The transmit data length is fixed at 8 bits If bit 2 ST1MPC is 0 data is transmitted and i...

Page 285: ...1MST indicates a bit that is not provided 1 is read if a read instruction is executed ST1MD SCI1 Transmit Operation Mode 1 0 0 0 UART normal mode 0 1 UART multiprocessor communication mode 1 0 Synchro...

Page 286: ...If SCI1 receives in UART synchronous multiprocessor communication mode bit 2 SR1MPC specifies which is received data or an address The receive data is 8 bit data length If bit 2 SR1MPC is 0 data is re...

Page 287: ...ed 1 is read if a read instruction is executed SR1MD SCI1 Receive Operation Mode 1 0 0 0 UART normal mode 0 1 UART multi processor communication mode 1 0 Synchronous normal mode 1 1 Synchronous multip...

Page 288: ...eive registers are two 8 bit shift registers that actually per form shift operations during a transmit receive operation The transmit and receive registers and transmit receive buffer register S1BUF h...

Page 289: ...rocessor communication mode This means that if the MPC bit of the data that is transferred when the SR1MPC bit of SR1CON is 0 is 1 MERR1 is set interpreting this as a multiprocessor communication erro...

Page 290: ...essor communication error no 1 SCI1 multiprocessor communication error yes 0 SCI1 receive ready interrupt request generation disabled 1 SCI1 receive ready interrupt request generation enabled 0 SCI1 r...

Page 291: ...e transmit side Figure 15 12 shows the configuration of ST2CON Description of Each Bit ST2MD bit 0 This bit specifies the transmit operation mode of SCI2 ST2MPC bit 2 If SCI2 transmits in UART multipr...

Page 292: ...MD 7 6 5 4 3 2 1 0 indicates a bit that is not provided 1 is read if a read instruction is executed 0 SCI2 UART normal mode 1 SCI2 UART multiprocessor communication mode 0 Data transmitted 1 Address t...

Page 293: ...es in UART multiprocessor communication mode this bit specifies which is received data or an address The receive data length is 8 bits If this bit is 0 data is received and if 1 an address is received...

Page 294: ...that is not provided 1 is read if a read instruction is executed 0 SCI2 UART normal mode 1 SCI2 UART multiprocessor communication mode 0 Data is received 1 Address is received 0 1 0 1 0 1 Multiproces...

Page 295: ...received data when the SR2EXP bit of SR2CON is set to 1 4 stage buffer mode These registers are read only and cannot be written to During the 4 stage buffer mode at the completion of each 1 byte recep...

Page 296: ...its of S2STAT0 by the program when a receive ends The contents of S2BUF0 must be read before resetting OERR20 bit 1 of the low order 4 bits of S2STAT0 Otherwise the OERR20 flag is set to 1 again irres...

Page 297: ...UART multi processor communication mode This means that if the MPC bit of the data that is transferred when the SR2MPC bit of SR2CON is 0 is 1 MERR20 is set inter preting this as a multiprocessor com...

Page 298: ...UF0 parity error yes 0 S2BUF0 multiprocessor communication error no 1 S2BUF0 multiprocessor communication error yes 0 S2BUF0 receive ready interrupt request generation disabled 1 S2BUF0 receive ready...

Page 299: ...t when the RES signal is input the BRK instruction is executed the watchdog timer is overflown or an operation code trap is generated S2STAT1 becomes 11H Figure 15 15 shows the configuration of S2STAT...

Page 300: ...bit of SR2CON is 0 is 1 MERR22 is set to 1 interpreting this as a multiprocessor communication error Figure 15 15 Configuration of S2STAT1 7 MERR22 6 PERR22 5 OERR22 4 3 MERR21 2 PERR21 1 OERR21 0 0 1...

Page 301: ...e buffer into which data will be transferred S2BUF0 S2BUF1 S2BUF2 S2BUF3 can be verified by reading bits 4 and 5 of S2STAT2 At reset when the RES signal is input the BRK instruction is executed the wa...

Page 302: ...or yes 0 1 0 1 S2BUF3 multiprocessor communication error no S2BUF3 multiprocessor communication error yes S2BUF3 parity error no S2BUF3 parity error yes BFCU2 1 Buffer counter monitor during SCI2 4 st...

Page 303: ...bled and if 0 generation is disabled RV2IE2 bit 2 This bit enables or disables the generation of SCI2 S2BUF2 receive ready interrupt requests If this bit is 1 generation is enabled and if 0 generation...

Page 304: ...on enabled 0 1 S2BUF3 receive ready interrupt request generation disabled S2BUF3 receive ready interrupt request generation enabled 0 1 S2BUF0 receive ready generation no see note S2BUF0 receive ready...

Page 305: ...e transmit side Figure 15 18 shows the configuration of ST3CON Description of Each Bit ST3MD bit 0 This bit specifies the transmit operation mode of SCI3 ST3MPC bit 2 If SCI3 transmits in UART multipr...

Page 306: ...MD 7 6 5 4 3 2 1 0 indicates a bit that is not provided 1 is read if a read instruction is executed 0 SCI3 UART normal mode 1 SCI3 UART multiprocessor communication mode 0 Data transmitted 1 Address t...

Page 307: ...receives in UART multiprocessor communication mode this bit specifies which is received data or an address The receive data length is 8 bits If this bit is 0 data is received and if 1 an address is r...

Page 308: ...that is not provided 1 is read if a read instruction is executed 0 SCI3 UART normal mode 1 SCI3 UART multiprocessor communication mode 0 Data is received 1 Address is received 0 1 0 1 0 1 Multiproces...

Page 309: ...received data when the SR3EXP bit of SR3CON is set to 1 4 stage buffer mode These registers are read only and cannot be written to During the 4 stage buffer mode at the completion of each 1 byte rece...

Page 310: ...its of S3STAT0 by the program when a receive ends The contents of S3BUF0 must be read before resetting OERR30 bit 1 of the low order 4 bits of S3STAT0 Otherwise the OERR30 flag is set to 1 again irres...

Page 311: ...UART multi processor communication mode This means that if the MPC bit of the data that is transferred when the SR3MPC bit of SR3CON is 0 is 1 MERR30 is set inter preting this as a multiprocessor com...

Page 312: ...UF0 parity error yes 0 S3BUF0 multiprocessor communication error no 1 S3BUF0 multiprocessor communication error yes 0 S3BUF0 receive ready interrupt request generation disabled 1 S3BUF0 receive ready...

Page 313: ...t when the RES signal is input the BRK instruction is executed the watchdog timer is overflown or an operation code trap is generated S3STAT1 becomes 11H Figure 15 21 shows the configuration of S3STAT...

Page 314: ...bit of SR3CON is 0 is 1 MERR32 is set to 1 interpreting this as a multiprocessor communication error Figure 15 21 Configuration of S3STAT1 7 MERR32 6 PERR32 5 OERR32 4 3 MERR31 2 PERR31 1 OERR31 0 0 1...

Page 315: ...e buffer into which data will be transferred S3BUF0 S3BUF1 S3BUF2 S3BUF3 can be verified by reading bits 4 and 5 of S3STAT2 At reset when the RES signal is input the BRK instruction is executed the wa...

Page 316: ...or yes 0 1 0 1 S3BUF3 multiprocessor communication error no S3BUF3 multiprocessor communication error yes S3BUF3 parity error no S3BUF3 parity error yes BFCU3 1 Buffer counter monitor during SCI3 4 st...

Page 317: ...bled and if 0 generation is disabled RV3IE2 bit 2 This bit enables or disables the generation of SCI3 S3BUF2 receive ready interrupt requests If this bit is 1 generation is enabled and if 0 generation...

Page 318: ...on enabled 0 1 S3BUF3 receive ready interrupt request generation disabled S3BUF3 receive ready interrupt request generation enabled 0 1 S3BUF0 receive ready generation no see note S3BUF0 receive ready...

Page 319: ...e transmit side Figure 15 24 shows the configuration of ST4CON Description of Each Bit ST4MD bit 0 This bit specifies the transmit operation mode of SCI4 ST4MPC bit 2 If SCI4 transmits in UART multipr...

Page 320: ...7 6 5 4 3 2 1 0 indicates a bit that is not provided 1 is read if a read instruction is executed 0 SCI4 UART normal mode 1 SCI4 UART multiprocessor communication mode 0 Data is transmitted 1 Address i...

Page 321: ...receives in UART multiprocessor communication mode this bit specifies which is received data or an address The receive data length is 8 bits If this bit is 0 data is received and if 1 an address is r...

Page 322: ...that is not provided 1 is read if a read instruction is executed 0 SCI4 UART normal mode 1 SCI4 UART multiprocessor communication mode 0 Data is received 1 Address is received 0 1 0 1 0 1 Multiproces...

Page 323: ...received data when the SR4EXP bit of SR4CON is set to 1 4 stage buffer mode These registers are read only and cannot be written to During the 4 stage buffer mode at the completion of each 1 byte rece...

Page 324: ...its of S4STAT0 by the program when a receive ends The contents of S4BUF0 must be read before resetting OERR40 bit 1 of the low order 4 bits of S4STAT0 Otherwise the OERR40 flag is set to 1 again irres...

Page 325: ...UART multi processor communication mode This means that if the MPC bit of the data that is transferred when the SR4MPC bit of SR4CON is 0 is 1 MERR40 is set inter preting this as a multiprocessor com...

Page 326: ...UF0 parity error yes 0 S4BUF0 multiprocessor communication error no 1 S4BUF0 multiprocessor communication error yes 0 S4BUF0 receive ready interrupt request generation disabled 1 S4BUF0 receive ready...

Page 327: ...t when the RES signal is input the BRK instruction is executed the watchdog timer is overflown or an operation code trap is generated S4STAT1 becomes 11H Figure 15 27 shows the configuration of S4STAT...

Page 328: ...it of SR4CON is 0 is 1 MERR42 is set to 1 interpreting this as a multiprocessor communication error Figure 15 27 Configuration of S4STAT1 7 MERR42 6 PERR42 5 OERR42 4 3 MERR41 2 PERR41 1 OERR41 0 0 1...

Page 329: ...e buffer into which data will be transferred S4BUF0 S4BUF1 S4BUF2 S4BUF3 can be verified by reading bits 4 and 5 of S4STAT2 At reset when the RES signal is input the BRK instruction is executed the wa...

Page 330: ...or yes 0 1 0 1 S4BUF3 multiprocessor communication error no S4BUF3 multiprocessor communication error yes S4BUF3 parity error no S4BUF3 parity error yes BFCU4 1 Buffer counter monitor during SCI4 4 st...

Page 331: ...bled and if 0 generation is disabled RV4IE2 bit 2 This bit enables or disables the generation of SCI4 S4BUF2 receive ready interrupt requests If this bit is 1 generation is enabled and if 0 generation...

Page 332: ...on enabled 0 1 S4BUF3 receive ready interrupt request generation disabled S4BUF3 receive ready interrupt request generation enabled 0 1 S4BUF0 receive ready generation no see note S4BUF0 receive ready...

Page 333: ...l M1S1 that indicates the beginning of an instruction execution and the interrupt request flag QSCIn is set to 1 When STnFREE becomes L level a start bit is generated synchronizing with the fall of th...

Page 334: ...13 14 15 16 1 2 3 4 5 6 7 START BIT D LSB D MSB PARITY BIT STOP BIT STOP BIT NEXT START BIT Explanation of Symbols BRGn 1 16 BRGn STnCLK CLK WSnBUF LSTnSF STnFREE TXDn pin M1S1 TXnREADY n 0 4 clock p...

Page 335: ...on and the interrupt request flag QSCI1 is set to 1 When ST1FREE becomes L level the transmit shift clock is output from the TXC1 pin in synchronization with the falling edge of the second ST1CLK and...

Page 336: ...ed by 1 4 transmit shift clock transmit shift clock output from pin P6_5 master clock write signal to S1BUF transmit start signal signal that indicates transmitting 0 transmit data output from pin P6_...

Page 337: ...ted synchronizing with the signal M1S1 that indicates the beginning of an instruction execution and the interrupt request flag QSCI1 is set to 1 When ST1FREE becomes L level at the rising edge of next...

Page 338: ...in TXD1 pin M1S1 TX1READY D LSB D bit 1 D MSB PARITY BIT D LSB Explanation of Symbols CLK TXC1 pin Edge detection ST1CLK WS1BUF LST1SF ST1FREE TXD1 pin M1S1 TX1READY master clock transmit shift clock...

Page 339: ...bit is judged as invalid and the receive operation is initialized SRnFREE becomes H level and then stops Receive data is sampled by 3 sampling clocks of the 1 16 division 7th 8th and 9th and 2 or mor...

Page 340: ...t START BIT D LSB D MSB PARITY BIT STOP BIT STOP BIT NEXT START BIT D LSB 1 16 counter start 1 16 counter stop Explanation of Symbols BRGn Sampling CLKn CLK Edge detection LSRnBUF RXnREADY clock pulse...

Page 341: ...from the RXC1 pin according to the specifica tion of SR1CON and receive data is sequentially shifted in the receive register If the final output of the receive shift clock ends the receive end signal...

Page 342: ...C1 pin receive shift clock output from pin P6_4 INRXD receive data sampled from RXD1 by the RXD sampling clock signal that indicates beginning of an instruction M1S1 Sampling CLK1 WSR1CON SR1FREE sign...

Page 343: ...ive shift clock finally rises SR1CLK acquired by edge detection is generated and the final receive data is input Then 1 CLK later the receive end signal LSR1BUF is generated If LSR1BUF is generated th...

Page 344: ...ation of Symbols CLK RXC1 pin Edge detection SR1CLK Sampling CLK1 master clock receive shift clock input from pin P6_4 receive shift clock in which RXC1 pin input edge is detected by CLK receive shift...

Page 345: ...ve shift clock write signal to SR1CON signal that indicates receiving 0 receive data input from pin P6_2 receive end signal receive interrupt request signal Explanation of Symbols Sampling CLK1 CLK SR...

Page 346: ...process that data by an interrupt since the 3 bytes of data will be received in the order of S0BUF3 S0BUF0 and S0BUF1 enable interrupt generation only for S0BUF1 the last buffer to receive data and t...

Page 347: ...on of Symbols Data 1 Data 2 Data 3 Data 4 Data 5 Data 1 Data 2 Data 3 Data 4 Data 5 1 frame 1 frame 1 frame 1 frame 1 frame LSRnBUF receive end signal RXnREADY receive interrupt request signal RxDn pi...

Page 348: ...A D Converter Functions Chapter 16 16...

Page 349: ......

Page 350: ...erated A successive approximation method using the Sample Hold function is utilized to convert analog quantities to digital quantities The converted result is stored in the A D result registers ADCR0...

Page 351: ...nterrupt Request Selector Analog Selector Figure 16 1 Configuration of A D Converter 0 ADC0 For A D converter specifications see Chapter 25 Electrical Characteristics Figure 16 2 Configuration of A D...

Page 352: ...D Result Register 13 Undefined ADCR13 A D Result Register 14 Undefined ADCR14 A D Result Register 15 Undefined ADCR15 A D Result Register 16 Undefined ADCR16 A D Result Register 17 Undefined ADCR17 A...

Page 353: ...or A D converter 1 is specified and A D conversion is performed for the specified channel The select mode is mainly controlled by the A D control register H ADCON0H ADCON1H It is also possible to oper...

Page 354: ...erflow 12 CAP15 event generation 13 FTM16 event generation 14 FTM17 event generation 15 Soft 0 bit 0 of ADHSCON set by the program 16 Soft 1 bit 1 of ADHSCON set by the program Interrupt Cause The A D...

Page 355: ...ode interrupt source as the ongoing A D conversion is generated the ongoing A D conver sion is given priority and the generated A D conversion request is ignored Figure 16 4 shows the configuration of...

Page 356: ...cifies the A D conversion start factor in scan mode If this bit is 0 the next conversion starts when the A D conversion is over If this bit is 1 1 channel A D conversion starts at each valid edge of t...

Page 357: ...ts at valid edge of INT1 0 Next conversion starts when cycle is completed 1 Conversion stops when cycle is completed 0 0 1 0 1 0 ch10 ch11 1 0 1 1 ch11 1 1 Setting inhibited ADCON0L SCNC0 bit 6 This b...

Page 358: ...rsion start factor in scan mode If this bit is 0 the next conversion starts when the A D conversion is over If this bit is 1 1 channel A D conversion starts at each valid edge of the external interrup...

Page 359: ...that setting ADRUN1 to 1 again by the program does not start A D conver sion again Figure 16 6 Configuration of ADCON1L SCNC1 SNEX1 ADRUN1 ADSNM13 ADSNM12 ADSNM11 ADSNM10 7 6 5 4 3 2 1 0 indicates a b...

Page 360: ...t mode Change the select channel after setting STS0 bit 4 to 0 When STS0 is 1 when A D conversion is running in select mode changing the select channel is invalid STS0 bit 4 This bit specifies RUN STO...

Page 361: ...s read if a read instruction is executed ADSTM0 A D Converter 0 Select Channel 3 2 1 0 0 0 0 0 ch0 0 0 0 1 ch1 0 0 1 0 ch2 0 0 1 1 ch3 0 1 0 0 ch4 0 1 0 1 ch5 0 1 1 0 ch6 0 1 1 1 ch7 1 0 0 0 ch8 1 1 c...

Page 362: ...t mode Change the select channel after setting STS1 bit 4 to 0 When STS1 is 1 when A D conversion is running in select mode changing the select channel is invalid STS1 bit 4 This bit specifies RUN STO...

Page 363: ...d if a read instruction is executed ADSTM1 A D Converter 1 Select Channel 3 2 1 0 0 0 0 0 ch12 0 0 0 1 ch13 0 0 1 0 ch14 0 0 1 1 ch15 0 1 0 0 ch16 0 1 0 1 ch17 0 1 1 0 ch18 0 1 1 1 ch19 1 0 0 0 ch20 1...

Page 364: ...ion in select mode If this bit is 1 A D conversion has ended This bit must be reset to 0 by the program ADSNIE0 bit 2 This bit specifies enable disable of an interrupt request generation when a scan c...

Page 365: ...e end yes 0 Interrupt request generation by INTSN0 disabled 1 Interrupt request generation by INTSN0 enabled 0 Interrupt request generation by INTST0 disabled 1 Interrupt request generation by INTST0...

Page 366: ...sion in select mode If this bit is 1 A D conversion has ended This bit must be reset to 0 by the program ADSNIE1 bit 2 This bit specifies enable disable of an interrupt request generation when a scan...

Page 367: ...de end yes 0 Interrupt request generation by INTSN1 disabled 1 Interrupt request generation by INTSN1 enabled 0 Interrupt request generation by INTST1 disabled 1 Interrupt request generation by INTST1...

Page 368: ...cannot be executed At reset when the RES signal is input the BRK instruction is executed the watchdog timer is overflown or an operation code trap is generated ADHSEL0 becomes 0000H Description of Eac...

Page 369: ...ion GTMC GEVC overflow CAP15 event generation FTM16 event generation FTM17 event generation Software 0 ADHSCON bit 0 set Software 1 ADHSCON bit 1 set 0 1 0 1 0 1 0 1 7 6 5 A D Hard Select Mode Activat...

Page 370: ...on GTMC GEVC overflow CAP15 event generation FTM16 event generation FTM17 event generation Software 0 ADHSCON bit 0 set Software 1 ADHSCON bit 1 set 0 1 0 1 0 1 0 1 15 14 13 A D Hard Select Mode Activ...

Page 371: ...annot be executed At reset when the RES signal is input the BRK instruction is executed the watchdog timer is overflown or an operation code trap is generated ADHSEL1 becomes 0000H Description of Each...

Page 372: ...GTMC GEVC overflow CAP15 event generation FTM16 event generation FTM17 event generation Software 0 ADHSCON bit 0 set Software 1 ADHSCON bit 1 set 0 1 0 1 0 1 0 1 7 6 5 A D Hard Select Mode Activation...

Page 373: ...GTMC GEVC overflow CAP15 event generation FTM16 event generation FTM17 event generation Software 0 ADHSCON bit 0 set Software 1 ADHSCON bit 1 set 0 1 0 1 0 1 0 1 15 14 13 A D Hard Select Mode Activat...

Page 374: ...lect mode the next A D conversion is reserved and will start after the present A D conversion is completed If 1 is written to bit 1 and bit 0 simultaneously A D conversion in the hard select mode due...

Page 375: ...ed and if 0 disabled ADHENC2 bit 2 This bit enables or disables hard select A D conversion on channel 2 If this bit is 1 the hard select of channel 2 is enabled and if 0 disabled ADHENC3 bit 3 This bi...

Page 376: ...0 1 ch1 hard select mode disabled ch1 hard select mode enabled 0 1 ch2 hard select mode disabled ch2 hard select mode enabled 0 1 ch3 hard select mode disabled ch3 hard select mode enabled 0 1 ch12 h...

Page 377: ...8 bits of data are all read as 1s At reset when the RES signal is input the BRK instruction is executed the watchdog timer is overflown or an operation code trap is generated ADCR0 ADCR23 are undefine...

Page 378: ...the case when the A D hard select mode is activated with the same trigger for ch0 and ch1 When A D hard select modes of different priority levels ch0 ch1 are activated by the same edge A D conversion...

Page 379: ...is re sumed Master clock CLK Select mode Scan mode Suspend Select mode Scan mode Resume Scan mode Select mode Interrupt request generation valid edge Hard select mode Hard select mode Completion 1 cl...

Page 380: ...Interrupt request generation valid edge ch1 Completion Completion b ch0 high priority request is generated after ch1 low priority activation When a high priority hard select mode activation request is...

Page 381: ...16 32 MSM66591 ML66592User sManual Chapter 16 A D Converter Functions...

Page 382: ...Transition Detector Functions Chapter 17 17...

Page 383: ......

Page 384: ...configuration of TRNSCON high order bits 17 Transition Detector Functions The MSM66591 ML66592 have eight transition detector functions which detect the valid edges rise fall both edges of an input p...

Page 385: ...Rising edge 1 1 Both edges Valid edge of TRNS2 5 4 0 Falling edge 1 0 Rising edge 1 1 Both edges Valid edge of TRNS3 7 6 0 Falling edge 1 0 Rising edge 1 1 Both edges 7 TRNSCON bits 0 7 13 12 11 10 9...

Page 386: ...the correspond ing bit of TRNSIT to 0 Figure 17 3 shows the configuration of TRNSIT TRNSF7 TRNSF6 TRNSF5 TRNSF4 TRNSF3 TRNSF2 TRNSF1 TRNSF0 7 6 5 4 3 2 1 0 0 Valid edge not input to TRNS0 pin 1 Valid...

Page 387: ...17 4 MSM66591 ML66592User sManual Chapter 17 Transition Detector Functions...

Page 388: ...Peripheral Functions Chapter 18 18...

Page 389: ......

Page 390: ...he master clock The master clock CLK is the frequency generated by multiplying the original oscillation clock by 2 2 3 CLK is only available in the MSM66591 If the CLKOUT pin is used bit 6 of the Port...

Page 391: ...2 1 0 CKOUT CLKOUT Pin Output Clock 2 0 1 2 CLK 0 1 4 CLK 0 1 8 CLK 0 1 16 CLK 0 RES pin did not become L level 1 RES pin became L level 0 OE pin L level 1 OE pin H level 1 2 3 CLK MSM66591 only 1 1...

Page 392: ...External Interrupt Request Function Chapter 19 19...

Page 393: ......

Page 394: ...ter to 1 A dedicated pin pin 1 is provided for NMI The valid edge of INT0 INT1 and INT2 can be specified using the external interrupt control register EXICON The valid edge of NMI can be specified usi...

Page 395: ...a read instruction is executed EXICON EX2M Valid Edge of INT2 1 0 0 0 L level 0 1 Falling edge 1 0 Rising edge 1 1 Both edges Figure 19 1 Configuration of EXICON Figure 19 2 Configuration of NMICON NM...

Page 396: ...Interrupt Request Processing Function Chapter 20 20...

Page 397: ......

Page 398: ...Register 11 3C or BC C0 C0 00 00 00 00 00 00 00 00 C0 00 00 00 00 C0 00 00 00 00 Interrupt Request Register 1 Interrupt Enable Register 1 Interrupt Priority Control Register 00 NMI Control Register E...

Page 399: ...esses which include Saving program counter PC Saving accumulator ACC Saving local register base LRB Saving program status word PSW Resetting the NMI request flag Disabling maskable interrupt acceptanc...

Page 400: ...tion 07F5H 07F6H 07F7H 07F8H 07F9H 07FAH 07FBH 07FFH 07F7H 07F8H 07F9H 07FAH 07FBH 07FCH 07FDH 07FFH PSWH LRBL LRBH ACCL ACCH CSR Undefined PCH 07F7H 07F8H 07F9H 07FAH 07FBH 07FCH 07FDH 07FFH PSWH LRB...

Page 401: ...rupts t Flag MIPF that enables disables all priorities y Register IPX0 IPX1 that sets the priority level Figure 20 2 shows a conceptual diagram of maskable interrupt control Table 20 2 lists the vecto...

Page 402: ...PW23 QSCI0 QINT1 IRQ P0INT0 P0TM0OV P0TM1OV P0CAP0 P0CAP1 P0CAP2 P0CAP3 P0RTO4 P0RTO5 P0RTO6 P0RTO7 P0RTO8 P0RTO9 P0RTO10 P0RTO11 P0SCI1 P0STMOV P0GTMOV P0AD1 P0AD0 P0PW01 P0PW23 P0SCI0 P0INT1 IPX0 IE...

Page 403: ...nterrupt is accepted A bit of IRQ can be set to 1 or 0 by the program At reset when the RES signal is input the BRK instruction is executed the watchdog timer is overflown or an operation code trap is...

Page 404: ...flown or an operation code trap is generated IP00L IP00H IP10L IP10H IP01L IP01H IP11L and IP11H become 00H and IP20L and IP21L become C0H 6 Interrupt Priority Control Register IPX0 IP00L IP00H IP10L...

Page 405: ...generation request is sent to the judgment logic of an interrupt priority and if the priority of the interrupt to be requested is higher than the highest priority of the interrupt in execution the int...

Page 406: ...ROM of MEMSCON to 1 17 cycles are required be cause cycles required to save the code segment register CSR are added When an interrupt generation condition is fulfilled by setting IRQ IE IP or MIPF to...

Page 407: ...20 10 MSM66591 ML66592User sManual Chapter 20 Interrupt Request Processing Function...

Page 408: ...Bus Port Functions Chapter 21 21...

Page 409: ......

Page 410: ...vice versa if the EA pin is at L level 21 1 1 Operation of P0 P1 P12_0 and P12_1 During a Program Memory Access When the internal program memory is accessed EA pin is at H level P0 P1 P12_0 and P12_1...

Page 411: ...P0_0 P0_7 P7_2 ALE A8 A16 P1_0 P1_7 P12_0 P7_3 PSEN O0 O7 A0 A7 A8 A16 OE CE MSM66591 External ROM 128K bytes MAX Latch Circuit Note Since in the ML66592 address 17 A17 is output from the P12_1 pin co...

Page 412: ...7 is the same as A8 A16 Figure 21 2 External Program Memory Access Timing No Wait Cycles P7_2 ALE CLK P7_3 PSEN AD0 AD7 P0_0 P0_7 A8 A16 P1_0 P1_7 P12_0 PC8 16 PC0 7 PC8 16 INST0 7 PC0 7 Number of wai...

Page 413: ...21 4 MSM66591 ML66592User sManual Chapter 21 Bus Port Functions...

Page 414: ...Expansion Port Chapter 22 22...

Page 415: ......

Page 416: ...B The data length is selectable as 8 bits or 16 bits Connection of devices such as a 74HC165 is assumed for external input and a 74HC595 is assumed for external output of the expansion port Because ex...

Page 417: ...iption of Each Bit EXPBUSY bit 0 This BUSY flag indicates that a data transfer is in progress This bit is read only and writes are ignored DATMOD bit 1 This bit specifies the bit length of the data tr...

Page 418: ...s assumed that a 74HC165 or other shift register is connected externally Reading EXPTD causes the transfer input to start and the EXPBUSY flag to change to 1 When EXPTD is read the latch strobe SFTSTB...

Page 419: ...t data is output in sync with the fall of the shift clock SFTCLK It is assumed that data is captured externally in sync with the rise of SFTCLK When SFTCLK outputs 8 clocks the transfer output is comp...

Page 420: ...Serial Port with FIFO SCI5 Chapter 23 23...

Page 421: ......

Page 422: ...lect pin P5_4 CS a read and write control pin P5_3 RWB a WAIT pin P5_7 WAIT with BUSY signal input and an interrupt input pin P5_5 INT2 are provided for use with the CAN controller If SCI5 is to be us...

Page 423: ...ialization this flag is automatically cleared This flag is used to initialize the FIFO pointer when commu nication is cut off S5EXIE bit 5 This flag enables or disables the generation of interrupt req...

Page 424: ...0 0 1 0 1 1 1 0 1 0 1 0 1 0 1 0 1 Interrupt request due to SCI5 receive completion disabled Interrupt request due to SCI5 receive completion enabled Interrupt request due to SCI5 transmit completion d...

Page 425: ...t is automatically cleared If this bit is cleared during a reception the reception is immediately suspended and SCI5 is initialized TENT bit 5 This flag starts transmission Setting this bit to 1 will...

Page 426: ...individual interrupt request flag becomes 1 Because this flag is not automatically cleared even when an interrupt is processed it must be cleared by the program S5TIRQ bit 7 When SCI5 transmission is...

Page 427: ...When the CAN controller is to be accessed for both transmission and reception the address written to SFADR is output from the SDOUT pin and then the data transmis sion or reception is performed At res...

Page 428: ...s overflown or an operation code trap is generated SFDIN becomes undefined Figure 23 6 shows the configuration of SFDIN Figure 23 7 SFDOUT Configuration Figure 23 6 SFDIN Configuration 23 7 Serial Dat...

Page 429: ...addresses beginning with the leading address that was transmitted first If the TENT bit is reset to 0 during a transfer the transmission is immediately sus pended and SCI5 initialized In this case the...

Page 430: ...A7 A0 A1 A2 A3 A4 A5 A6 A7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D0 D1 D2 D3 D4 D5 D6 D7 D1 D2 D3 SDIN R W CS SCLK SDOUT SDIN R W Address transmission Address reception BUSY reception WAIT input BUSY output Dat...

Page 431: ...23 10 MSM66591 ML66592User sManual Chapter 23 Serial Port with FIFO SCI5...

Page 432: ...RAM Monitor Function Chapter 24 24...

Page 433: ......

Page 434: ...the RAM monitor function In the MSM66Q591 ML66Q592 flash EEPROM version the RAM monitor function cannot be used in the user mode used for reprogramming the flash EEPROM 24 1 Configuration of RAM Monit...

Page 435: ...r Configuration RAM Address Pointer Program Counter Comparator Comparator RAM Address Buffer ROM Address Buffer RAM Data Register 21 bit Shift Register DIN P11_0 RMRX TEST for MSM66591 ML66592 EA for...

Page 436: ...or ROM address reception RAM address field bit 0 to bit 15 when setting a RAM address Sets the RAM address desired to be read ROM address field bit 0 to bit 17 when setting a ROM address Sets the ROM...

Page 437: ...LK RMRX bit 2 bit 1 bit 13 bit 14 bit 15 bit 16 bit 17 0 0 0 1 ENABLE GO bit 0 ROM address 18 bits MODE bit RMCLK RMTX bit 2 bit 1 bit 13 bit 14 bit 15 0 0 0 0 0 bit 0 RAM data 16 bits Dummy bits 1 RA...

Page 438: ...data desired to be read Set a ROM address in accordance with the ROM address setting timing diagram of Figure 24 2 2 Set MODE bit 1 ENABLE bit 1 and GO bit 1 When the RAM monitor function detects tha...

Page 439: ...RAM monitor function is disabled and the control circuit is initialized In the MSM66591 ML66592 when the TEST pin is brought back to a L level the RAM monitor function is disabled and the control cir...

Page 440: ...a register 0000H 5555H AAAAH Explanation of Symbols PCCMP RAMCMP A rise in this signal indicates that the set ROM address has matched the program counter A rise in this signal indicates that the set R...

Page 441: ...24 8 MSM66591 ML66592User sManual Chapter 24 RAM Monitor Function...

Page 442: ...25 Electrical Characteristics Chapter 25...

Page 443: ......

Page 444: ...ference voltage Analog input voltage VREF VHV 0 3 to VDD 0 3 and 0 3 to AVDD 0 3 0 3 to 13 25 Electrical Characteristics MSM66591 Electrical Characteristics 25 1 Absolute Maximum Ratings MSM66591 1 If...

Page 445: ...ature Fanout MHz fOSC 0 Hz 1 VDD AVDD 20 MHz fOSC 24 MHz 1 Flash ROM programming cycle 3 Ambient temperature during Flash ROM programming 3 Digital power supply voltage during Flash ROM programming 3...

Page 446: ...tage VOL IO 3 2 mA 0 4 1 4 L level output voltage IO 1 6 mA 0 4 2 Input leakage current Input leakage current IIH IIL 1 1 6 0 1 0 1 3 Input current VI VDD 0 V 1 250 A 5 Input current 15 15 7 H level o...

Page 447: ...Only for MSM66Q591 4 When programming data into Flash ROM using Oki s Flash ROM programmer or YDC s Flash ROM programmer use a resistor of 1 k or less if connecting an external resistor in series wit...

Page 448: ...3t W 10 4t W 3 High address hold time tAPH 0 t W 10 Instruction setup time tIS Instruction hold time tIH 0 t W 10 VDD 5 V 10 Ta 40 to 115 C 2 30 1 The master clock pulse is the frequency generated by...

Page 449: ...e impedance 10 Bit Resolution EL Linearity error ED Differential linearity error EZS LSB Zero scale error EFS Full scale error ECT Refer to the measurement circuit Figure 25 2 Crosstalk tCONV by ADTM...

Page 450: ...haracteristics Ideally the range of analog input voltage that corresponds to 1 converted bit of digital output is 1LSB VREF AGND 1024 Differential error is the difference between this ideal bit size a...

Page 451: ...age 2 Analog reference voltage Analog input voltage VREF VHV 0 3 to VDD 0 3 and 0 3 to AVDD 0 3 0 3 to 13 ML66592 Electrical Characteristics 25 6 Absolute Maximum Ratings ML66592 1 If this device is u...

Page 452: ...erature Fanout MHz fOSC 0 Hz 1 VDD AVDD 20 MHz fOSC 28 MHz 1 Flash ROM programming cycle 3 Ambient temperature during Flash ROM programming 3 Digital power supply voltage during Flash ROM programming...

Page 453: ...age VOL IO 3 2 mA 0 4 1 4 L level output voltage IO 1 6 mA 0 4 2 Input leakage current Input leakage current IIH IIL 1 1 6 0 1 0 1 3 Input current VI VDD 0 V 1 250 A 5 Input current 15 15 7 H level ou...

Page 454: ...EA Only for ML66Q592 4 When programming data into Flash ROM using Oki s Flash ROM programmer or YDC s Flash ROM programmer use a resistor of 1 k or less if connecting an external resistor in series wi...

Page 455: ...time tIS Instruction hold time tIH 0 t W 10 VDD 5 V 10 Ta 40 to 95 C 2 30 1 The master clock pulse is the frequency generated by multiplying the original oscillation clock by 2 2 If this device is us...

Page 456: ...ce impedance 10 Bit Resolution EL Linearity error ED Differential linearity error EZS LSB Zero scale error EFS Full scale error ECT Refer to the measurement circuit Figure 25 4 Crosstalk tCONV by ADTM...

Page 457: ...aracteristics Ideally the range of analog input voltage that corresponds to 1 converted bit of digital output is 1LSB VREF AGND 1024 Differential error is the difference between this ideal bit size an...

Page 458: ...Package Dimensions Chapter 26 26...

Page 459: ......

Page 460: ...ore you perform reflow mounting contact Oki s responsible sales person for the product name package name pin number package code and desired mounting conditions reflow method temperature and times 26...

Page 461: ...26 2 MSM66591 ML66592User sManual Chapter 26 Package Dimensions...

Page 462: ...Revision History Chapter 27 27...

Page 463: ......

Page 464: ...27 1 MSM66591 ML66592User sManual Chapter 27 Revision History 27 27 Revision History Document No Date Page Description FEUL66591 66592 01 First edition Mar 4 2002 Previous Edition Current Edition...

Page 465: ...27 2 MSM66591 ML66592User sManual Chapter 27 Revision History...

Page 466: ...nd intellectual property right etc is granted by us in connection with the use of the product and or the information and drawings contained herein No responsibility is assumed by us for any infringeme...

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