Oki MSM66591, User Manual

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23-8
MSM66591/ML66592 User's Manual
Chapter 23 Serial Port with FIFO (SCI5)
23.8 SCI5 Operation
During a data transfer, the clock selected by bits 0–2 of SCI5CON0 (S5CK0–S5CK2)
becomes the shift clock for SCI5 (SCI5 clock) and is output from the SCLK pin.
Transmit data is synchronized to the falling edge of the SCI5 clock and output LSB first
from the SDOUT pin. Receive data is synchronized to the rising edge of the SCI5 clock
and input LSB first from the SDIN pin. It is assumed that, regarding external devices,
the serial-in data (receive data) changes at the falling edge of the SCI5 clock and the
serial-out data (transmit data) is captured at the rising edge of the SCI5 clock.
When writing data to the CAN controller, write the leading transmit address (1 byte) to
the SCI5’s SFADR, and then write the transmit data (1–8 bytes) to the SFDOUT
register.
When the transmit enable flag (bit 5 of SCI5CON1: TENT) is set to "1", the
CS
(chip
select) pin and RWB (read/write) pin first change to "L" levels. Next, the leading ad-
dress (1 byte) is output from the SDOUT pin to the CAN controller. Then, the number of
bytes of data written to the SFDOUT register are transmitted from the SDOUT pin.
(There is an interval between address-data transfers and between data-data transfers.)
After all the data written to the SFDOUT register has been completely transmitted, the
CS
pin and RWB pin change to "H" levels, the TENT bit is reset to "0", and an interrupt
request flag (QSIO5) is set to "1" at the beginning of the next instruction (M1S1). In this
case, it is assumed that on the CAN controller side, transmit data has been written to
consecutive addresses beginning with the leading address that was transmitted first.
If the TENT bit is reset to "0" during a transfer, the transmission is immediately sus-
pended and SCI5 initialized. In this case, the transmission contents are not saved.
When reading data from the CAN controller, write the leading receive address (1 byte)
to the SCI5’s SFADR, and then write the number of receive data bytes (1–8 bytes) to
bits 0–3 of SCI5CON1 (S5RN0–S5RN3).
When the receive enable flag (bit 4 of SCI5CON1: TENR) is set to "1", the
CS
(chip
select) pin first changes to a "L" level. Next, the leading address (1 byte) is output from
the SDOUT pin to the CAN controller. Data is thereafter received from the SDIN pin
(there is an interval between data-data transfers). Received data is transferred in order
to the FIFO.
When the number of data bytes specified by S5RN0–S5RN3 are received, the recep-
tion is complete, the
CS
pin changes to a "H" level, the TENR bit is reset to "0", and an
interrupt request flag (QSCI5) is set to "1" at the beginning of the next instruction
(M1S1).
Data that was received and then transferred to the FIFO is read via the SFDIN register.
In this case, it is assumed that on the CAN controller side, receive data has been read
in consecutive addresses beginning with the leading address that was transmitted first.
If the TENR bit is reset to "0" during a reception, the reception is immediately sus-
pended and SIO5 initialized. In this case, the reception contents are not saved.
SCI5, when it has output leading address, checks the BUSY signal input to the WAIT
pin. If the WAIT pin is "1", it halts operation. SCI5 starts operation when the WAIT pin
changes to "0".
Figure 23-8-(a) shows the transmission operation timing during a consecutive transfer,
and Figure 23-8-(b) shows the reception operation timing during a consecutive transfer.