Oki MSM66591, User Manual

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5-3
MSM66591/ML66592 User's Manual
Chapter 5 Memory Control Functions
5
5.2 READY Function
The MSM66591/ML66592 can specify the wait cycle (ROM: 0 to 3 cycles) to insert during
external memory access, so that memory that has a slow access speed can be connected.
The ROM READY control register (ROMRDY) specifies the number of wait cycles.
ROMRDY specifies the wait cycle when the external memory is extended (or external ROM
mode is used) to the program memory space.
ROMRDY can be read/written by the program. If ROMRDY is written to, the low-order 2
bits are valid, but the high-order 6 bits become invalid. If ROMRDY is read, the low-
order 2 bits are valid, but "1" is read for the high-order 6 bits.
Figure 5-2 shows the configuration of ROMRDY.
At reset (when the
RES
signal is input, the BRK instruction is executed, the watchdog
timer is overflown, or an operation code trap is generated), both RAMRDY and
ROMRDY becomes FFH. Then if the external program memory is accessed, 3 cycles of
a wait cycle can be inserted.
[Note]
In the MSM66591/ML66592, unlike internal program memory access, when external
program memory is accessed, 1 cycle is automatically inserted per 1 byte access.
ROMRDY specifies the number of cycles inserted in addition to the above 1 cycle
inserted.
Figure 5-2 Configuration of ROMRDY
— — — — — — ORDY1 ORDY0
7 6 5 4 3 2 1 0
1 0
0 0
0 1
1 0
1 1
Additional cycles
to be inserted when
external program
memory is accessed
0 cycle
1 cycle
2 cycles
3 cycles
ORDY
"—" indicates a bit that is not provided.
"1" is read if a read instruction is executed.
1 cycle is 1 CLK.
ROMRDY