Oki MSM66591, User Manual

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15-70
MSM66591/ML66592 User's Manual
Chapter 15 Serial Port Functions
<Synchronous Normal Master Mode (SCI1 only)>
The clock pulse (BRG1), generated by the baud rate generator (S1TM), is divided by 4
to generate the transmit shift clock (ST1CLK) (refer to Figure 15-31).
The transmit circuit controls the transfer of transmit data synchronizing with ST1CLK.
The transmit operation is started with a signal to write transmit data to S1BUF,
(WS1BUF: write signal to S1BUF. For example, a signal that is output if "STB A,
S1BUF" is executed) as a trigger.
If WS1BUF is generated, a transmit start signal (LST1SF) is generated after 1 CLK
(master clock).
The content of S1BUF is transferred to the transmit register at the fall of LST1SF.
At this time, the transmit operation starts, and the ST1FREE signal that indicates
transmitting is set to "L" level.
Then a transmit interrupt (TX1READY) request is generated synchronizing with the
signal (M1S1) that indicates the beginning of an instruction execution, and the interrupt
request flag (QSCI1) is set to "1".
When ST1FREE becomes "L" level, the transmit shift clock is output from the TXC1 pin
in synchronization with the falling edge of the second ST1CLK, and at the rising edge of
next CLK, bit 0 (LSB first) of the transmit data is output from the TXD1 pin.
Hereafter, transmit data and a parity bit are added synchronizing with TXC1 (ST1CLK),
according to the specification of ST1CON, and a 1 frame transmission ends.
TXD1 changes immediately before the fall of TXC1 (variable according to the S1TM set
value and the original oscillation clock).
In this way the receive side fetches TXD1 at the rise of TXC1.
In this mode, the default level on TXD1 pin is "H" level (when the corresponding bit of
the port secondary function register = "1").
<Synchronous Multiprocessor Communication Master Mode (SCI1 only)>
In synchronous multiprocessor communication master mode, transmit is controlled by
the same timing as synchronous normal master mode. The differences are shown
below.
• An MPC bit ("1": address transmitted; "0": data transmitted) is added between the end
of data (MSB bit) and the parity bit.
[Note] SCI0, SCI2, SCI3, and SCI4 do not have synchronous mode.