Oki MSM66591, User Manual

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9-1
9
MSM66591/ML66592 User's Manual
Chapter 9 Time Base Counter (TBC)
9. Time Base Counter (TBC)
The MSM66591/ML66592 time base counter (TBC) is an 8-bit counter that uses as its
input clock an overflow of the 4-bit auto-reload timer. The 4-bit auto-reload timer uses
as its input the master clock pulse (CLK) generated by multiplying the original oscillation
clock by 2.
The divided output of the TBC is used as the reference clock for the flexible timer, the
timer for the serial port, and others.
The TBC is cleared to "0" at reset (when the
RES
signal is input, the BRK instruction is
executed, the watchdog timer (WDT) is overflown, or an operation code trap is gener-
ated), and from then on operates unless the supply of the original oscillation clock
stops.
Figure 9-1 shows the configuration of TBC.
Figure 9-1 Configuration of TBC
*1 CLK (" " in the above figure) used for TM0 and TM1 is supplied to the timer data
sequencer and to the timing controller of each timer register module.
*2 If the 1/n (4-bit) counter is set as n = 1, and if the TBCCLK is selected for TM0 and TM1,
the flexible timer does not operate normally. (However, the freerun counters TM0,
TM0L, and TM1 operate normally.)
TBCCLK
PWM
8-Bit Timer for SCI
TM0 (20-Bit Timer)
TM1 (16-Bit Timer)
General-Purpose 8-Bit Timer
1/n (4-bit)
TBC (9-bit)
WDT (9-bit)
Reset
by WDT
1/2
1/2 CLK
1/2 TBCCLK 1/4 TBCCLK 1/8 TBCCLK 1/16 TBCCLK 1/32 TBCCLK 1/64 TBCCLK 1/128 TBCCLK 1/256 TBCCLK
CLK
*2
*2
*1
*1
Multiplied
by 2
Original
Osc. Clock