Oki MSM66591, User Manual

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3-17
MSM66591/ML66592 User's Manual
Chapter 3 CPU Architecture
3
2 1 0
Setting of Pointing
Register
S C B
0 0 0 PR0 (0200H–0207H)
0 0 1 PR1 (0208H–020FH)
0 1 0 PR2 (0210H–0217H)
0 1 1 PR3 (0218H–021FH)
1 0 0 PR4 (0220H–0227H)
1 0 1 PR5 (0228H–022FH)
1 1 0 PR6 (0230H–0237H)
1 1 1 PR7 (0238H–023FH)
1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 0
LRBH LRBL
LRB
Figure 3-7 Configuration of LRB
[2] Program Counter (PC)
The PC is a 16-bit counter that holds the address information in the segment of the
program to be executed next. PC is normally incremented according to the number of
bytes of an instruction to-be-executed. If a branch instruction or an instruction that
requires a branch is executed, immediate data, register content, etc. are loaded.
The CSR value does not change even if an overflow occurs because of an increment in
PC.
At reset (when the
RES
signal is input, the BRK instruction is executed, the watchdog
timer is overflown, or an operation code trap is generated), or when an interrupt occurs,
the content of the vector table area is loaded to the PC.
[3] Local Register Base (LRB)
The LRB is a 16-bit register. The low-order 8 bits (LRBL) specifies 2K bytes of data
memory space, 0200H–09FFH, in 8 byte units (local register addressing).
The high-order 8 bits (LRBH) specify 64K bytes of data memory space in 256 byte units
(current page addressing). 64 bytes of the current page, xxC0H–xxFFH, is an area that
SB, RB, JBR, and JBS instructions can access by specifying the sba.bit addressing.
Both LRBL (02H) and LRBH (03H) are assigned to SFR, and the content is undefined
at reset (when the
RES
signal is input, the BRK instruction is executed, the watchdog
timer is overflown, or an operation code trap is generated).