Oki MSM66591, User Manual

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MSM66591/ML66592 User's Manual
Chapter 3 CPU Architecture
PSWL PSWH
PSW
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CY ZF HC DD S F2 OV MIE MAB F1
BCB
F0
SCB
1 0 2 1 0
Figure 3-6 Configuration of PSW
3.2.2 Control Register
Control registers are a group of registers that have dedicated functions, such as
functions for program status, program sequence, local registers, and stack control.
Control registers consist of four 16-bit registers.
[1] Program Status Word (PSW)
PSW is a 16-bit register that consists of
• flags to be referred to when executing an instruction (DD)
• flags that are set to "1" or "0" depending on the result of an executing instruction (CY,
ZF, HC, S, OV)
• flags to specify the pointing register set (SCB0–2)
• flags to specify enable ("1") or disable ("0") of an entire maskable interrupt (MIE)
• flags that the user can freely use (F0–2)
• flags available for future expansion of CPU core functions. The user can freely use
these flags in MSM66591/ML66592. (BCB0, 1, MAB)
PSW can be divided into PSWH (bits 8–15) and PSWL (bits 7–0) in 8-bit units, and can
perform 8-bit unit operations as well as 16-bit unit operations depending on the instruc-
tion.
Figure 3-6 shows the configuration of PSW.
High-order 8 bits (PSWH) of PSW include:
• flags to be referred to when executing an instruction (DD)
• flags that are set to "1" or "0" depending on the result of an executing instruction (CY,
ZF, HC, DD, S, OV)
This means that if the following instructions are executed to PSW or PSWH, the
operation may be different from the original operation of the flags.
A. PSW or PSWH content load instruction to ACC
(ZF becomes undefined)
B. Bit operation instruction to ZF (ZF becomes undefined)