Oki MSM66591, User Manual

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24-5
MSM66591/ML66592 User's Manual
Chapter 24 RAM Monitor Function
24
24.3 RAM Monitor Function Operation
To enable the RAM monitor function, set the
EA
pin to a "H" level for the MSM66Q591/
ML66Q592, and set the TEST pin to a "H" level for the MSM66591/ML66592. Do not
apply a high voltage (more than 5 V) to the
EA
and TEST pins of the MSM66591/
ML66592 mask ROM version, because those pins of the mask ROM version will be
damaged if a high voltage is applied to. Care must be taken especially when the mask
ROM version and the flash EEPROM version share the substrate. With this setting, the
secondary functions of P11_0 to P11_3 (RMRX, RMTX, RMCLK, and RMACK) will be
enabled. The operating modes (RESET, STOP, and HALT) of the microcontroller do not
affect operation of the RAM monitor function.
In the MSM66Q591/ML66Q592 flash EEPROM version, the RAM monitor function
cannot be used in the user mode used for reprogramming the flash EEPROM.
This RAM monitor function requires that two addresses be set, a RAM address and a
ROM address. Either address may be set first. The following example describes the
case in which the RAM address is set first.
[1] Setting the addresses
First, as shown in the RAM address setting timing diagram of Figure 24-2 (1), set the
RAM address desired to be read by inputting a serial input to the RMRX pin in accor-
dance with the synchronous clock RXCLK. (Set MODE bit = "0", ENABLE bit = "1", and
GO bit = "0".)
Next, determine the read timing for the RAM data desired to be read. Set a ROM
address in accordance with the ROM address setting timing diagram of Figure 24-2 (2).
(Set MODE bit = "1", ENABLE bit = "1", and GO bit = "1".)
When the RAM monitor function detects that the GO bit of the received ROM address is
"1", the ROM address is loaded in the ROM address buffer, and address comparison is
started.
[2] Detection of address matching
When data is written to the set RAM address, the same data is also loaded into the
RAM data register.
Next, when the program counter matches the set ROM address, the RMACK pin
changes from a "L" to a "H" level, and address comparison is halted until another
address whose GO bit is "1" is set. The RMACK pin remains at a "H" level until reading
of the RAM data is complete. If the program counter matches the ROM address before
matching the RAM address, as shown in Figure 24-4, the match with the ROM address
is ignored. On the other hand, if there is another match with the RAM address before a
match with the ROM address, as shown in Figure 24-5, the contents of the RAM data
register are updated.
[3] Reading data
After the RMACK pin changes to a "H" level, by inputting an external synchronous clock
to the RXCLK pin, contents of the RAM data register are read via the RMTX pin. The
RMACK pin changes to a "L" level when the read is complete.
Because a new address can be set from the RMRX pin at the same time as data is read
from the RMTX pin, reading can be restarted at a new address immediately after the
current read is complete. To restart at the same address (without changing the address
setting), set the ENABLE bit to "0" and only the GO bit to "1". (The values of the ad-
dress bits are arbitrary.)