Oki MSM66591, User Manual

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13-4
MSM66591/ML66592 User's Manual
Chapter 13 PWM Functions
13.1 Configuration of PWM
The MSM66591/ML66592 have 12 sets of PWM functions (PWM0–PWM11). PWM0–
PWM11 have the same configuration except for the SFR address.
PWM consists of 16-bit counters (PWC0–PWC11), 16-bit counter buffer registers
(PWC0BF–PWC11BF), 16-bit registers (PWR0–PWR11), 16-bit buffer registers
(PW0BF–PW11BF), a comparison circuit for PWC0–PWC11 and PWR0–PWR11, an
output F/F, and various control registers (PWINTQ0, PWINTQ1, PWINTE0, PWINTE1,
PWCON0–PWCON5 and PWRUN) that control operations.
If PWM0–PWM11 pins are used for PWM functions, set the corresponding bit of the
Port 7 and Port 8 secondary function control registers to "1". If the
OE
pin is in "L" level,
PWM0–PWM11 pins operate (outputs) as a PWM function, but if the
OE
pin is in "H"
level, PWM0–PWM11 pins go into high impedance status.
[1] PWM Counters (PWC0–PWC11)
PWC0–PWC11 are 16-bit down counters. The input clock can be selected from among
the master clock, TBCCLK, 1/2 TBCCLK, 1/4 TBCCLK, 1/8 TBCCLK, and 1/16
TBCCLK. If an underflow occurs when the corresponding PWnRUN bit is "1" and
PWC0–PWC11 are in count operations, the PWM counter generates an interrupt
request (PWC0 and PWC1, PWC2 and PWC3, PWC4 and PWC5, PWC6 and PWC7,
PWC8 and PWC9, PWC10 and PWC11 are common), and the contents of the 16-bit
PWM counter buffer register are loaded to the PWM counters. The PWM counter then
loads the content of the 16-bit PWM buffer register to the 16-bit PWM register, and sets
the output F/F to "1".
PWC0–PWC11 can be read, but cannot be written, by the program. However, if
PWC0BF–PWC11BF are written when the corresponding PWnRUN bit is "0" (stop
status), the 16-bit contents are written to PWC0–PWC11 as well.
At reset (when the
RES
signal is input, the BRK instruction is executed, the watchdog
timer is overflown, or an operation code trap is generated), PWC0–PWC11 become
FFFFH.
[2] PWM Counter Buffer Registers (PWC0BF–PWC11BF)
PWC0BF–PWC11BF are 16-bit registers for setting cycles (for storing the reload values
for PWC0–PWC11). If PWC0–PWC11 underflow, the contents of PWC0BF–PWC11BF
are loaded to the 16-bit PWM counter.
PWC0BF–PWC11BF can be read, but cannot be written, by the program. If PWC0BF–
PWC11BF are written to when the corresponding PWnRUN bit is "0" (stop status), the
contents of 16-bits are written to PWC0–PWC11 as well.
At reset (when the
RES
signal is input, the BRK instruction is executed, the watchdog
timer is overflown, or an operation code trap is generated), PWC0BF–PWC11BF
become FFFFH.