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Chip Errata for the i.MX 6Dual/6Quad and i.MX 6DualPlus/6QuadPlus, Rev. 6.1, 06/2016
10
NXP Semiconductors
MLB
MLB: Multi frame per sub-buffer mode is not supported
No fix scheduled
MMDC
MMDC: DDR Controller’s measure unit may return an incorrect value when operating
below 100 MHz
No fix scheduled
No fix scheduled
PCIe
PCIe: 9000436491—Reading the Segmented Buffer Depth Port Logic registers
returns all zeros
No fix scheduled
No fix scheduled
No fix scheduled
PCIe: 9000413207—PME Requester ID overwritten when two PMEs are received
consecutively
No fix scheduled
PCIe: 9000405932—AXI/AHB Bridge Slave does not return a response to an
outbound non-posted request
No fix scheduled
No fix scheduled
PCIe: 9000402443—Uncorrectable Internal Error Severity register bit has incorrect
default value
No fix scheduled
No fix scheduled
No fix scheduled
No fix scheduled
No fix scheduled
No fix scheduled
PCIe: 9000336356—Link configuration sometimes proceeds when incorrect TS
Ordered Sets are received
No fix scheduled
PCIe: 9000471173—Bad DLLP error status checking is too strict
No fix scheduled
PCIe: 9000493959—L1 ASPM incorrectly entered after link down event during L1
ASPM entry negotiation
No fix scheduled
PCIe: 9000470913—Power Management Control: Core might enter L0s/L1 before
Retry buffer is empty
No fix scheduled
Table 3. Summary of Silicon Errata (continued)
Errata
Name
Solution
Page