ERR003767
Chip Errata for the i.MX 6Dual/6Quad and i.MX 6DualPlus/6QuadPlus, Rev. 6.1, 06/2016
NXP Semiconductors
199
Description:
As stated in Section 5.2.2.6 of AHCI Specification:
“If increments of hCccComplete are targeted for the same cycle as the clearing of hCccComplete
to 0h, the final value shall be 0h. The additional completions are aggregated into the CCC interrupt
that will be signaled imminently.”
The core does not aggregate the additional completions into the same interrupt. When the device
returns an SDB FIS with multiple NCQ command completions (multiple SACT bits are cleared)
and CCC is enabled, if a subset of those multiple bits causes IS.CCC=1 interrupt, then the
remaining bits are still counted as completions through hCccComplete register increments,
possibly causing more IS.CCC interrupts to be generated.
Projected Impact:
IS.CCC interrupt might be generated more frequently if the device uses NCQ command
completion aggregation. The probability of this problem occurring is medium.
Workarounds:
None.
Proposed Solution:
No fix scheduled
Linux BSP Status:
Software workaround not implemented in Linux BSP. Functionality or mode of operation in which
the erratum may manifest itself is not used. IS.CCC is not used.
ERR003767
SATA: 9000446482—hCccComplete cleared, incorrectly incremented
