ERR004484
Chip Errata for the i.MX 6Dual/6Quad and i.MX 6DualPlus/6QuadPlus, Rev. 6.1, 06/2016
112
NXP Semiconductors
Description:
This issue causes a data alignment error under the following two corner case conditions:
• The last 16 bytes of the cache line are being sent to the memory controller when it is not ready
• The memory controller’s “Ready” signal is asserted for one cycle. It then reads 8 bytes of data
and then the “Ready” signal becomes de-asserted again.
In the design, the memory controller uses the address of the last 8 bytes as the address of the entire
cache line. When either of these conditions happens, the last 8 bytes of data are paired with the
address of the subsequent cache line, and the entire cache line gets written to the wrong location.
The likelihood of hitting this corner case is significantly reduced if the GPU3D core and shader
clocks run at the same frequency.
Projected Impact:
This issue only affects OpenCL applications by causing data corruption (incorrect data
calculations). This will not cause a system hang or screen corruption in 3D applications.
Workarounds:
None
Proposed Solution:
No fix scheduled
Linux BSP Status:
Workaround possible but not implemented in the BSP, impacting functionality as described above.
ERR004484
GPU3D: L1 cache “Write Address Data” pairing error [i.MX
6Dual/6Quad Only]
