ERR007575
Chip Errata for the i.MX 6Dual/6Quad and i.MX 6DualPlus/6QuadPlus, Rev. 6.1, 06/2016
NXP Semiconductors
175
Description:
When the remote link partner enters Recovery.rcvrlock from the L0 state and transmits only two
TS1 Ordered Sets (OS), the core can sometimes miss the second TS1 OS and therefore delay its
entry into Recovery.rcvrlock.
Scenario Setup:
The remote link partner enters Recovery.rcvrlock from the L0 state and transmits only two TS1
OS's
The remote link partner then unusually moves to ElecIdle and de-asserts the PIPE signal rxvalid in
Recovery.RcvrLock
The expected response from the core is that it will transition to Recovery.rcvrlock on receipt of the
two TS1 OS's
The core receives a SKP OS or EIEOS that was inserted between the two TS1 Ordered Sets.
Note: This is an unusual verification setup, and in a real system the remote partner must keep
sending TS1s in Recovery.RcvrLock and then core will move to Recovery after receiving 2 TS1s.
Projected Impact:
The core might miss the second TS1 OS because the remote partner only sent two TS1 OS's, the
core will not receive a second TS1 OS and therefore stays in L0.
The PHY detects a decode error and passes it to the core.
The core sends the error message to the remote link partner.
The core does not get a response from the remote partner and replays the message three times.
The replay timer rolls over (caused by unacknowledged ERR_CORR messages) and a link retrain
is requested.
The core moves to recovery.
Workarounds:
None
Proposed Solution:
No fix scheduled.
Linux BSP Status:
Software workaround cannot be implemented to mask or workaround this SoC issue. This erratum
will result in impacted or reduced functionality as described above.
ERR007575
PCIe: LTSSM delay when moving from L0 to recovery upon receipt of
insufficient TS1 Ordered Sets (9000514662)
