ERR005174
Chip Errata for the i.MX 6Dual/6Quad and i.MX 6DualPlus/6QuadPlus, Rev. 6.1, 06/2016
122
NXP Semiconductors
Description:
When the AHB Audio DMA is started, by setting to 1’b1 for the first time the register field
AHB_DMA_START.data_buffer_ready, the AHB Audio DMA will request data from the AHB
bus to fill its internal AHB DMA FIFO.It is possible that a AHB DMA FIFO read action occurs
during the time window between the first sample stored on the AHB DMA FIFO and when the
AHB DMA FIFO has stored, at least, the number of configured audio channels in samples. If this
happens, the AHB DMA FIFO will reply with samples that are currently on the AHB Audio FIFO
and will repeat the last sample after the empty condition is reached.
Projected Impact:
This will miss-align the audio stream, causing a shift in the distribution of audio on the channels
on the HDMI sink side, with no knowledge of the DWC_hdmi_tx enabled system.
Workarounds:
This procedure assumes that all of the buffers provided to the AHB audio DMA through the
AHB_DMA_STRADDR and AHB_DMA_STPADDR registers obey to the rule:
(AHB_DMA_STPADDR - AHB_DMA_1) == n x NumberOfChannelEnabled
Where n must be an integer.
Note that this is only a re-affirmation of a stated usage restriction of AHB audio DMA. The initial
ACR packets will contain a null N value but lab tests show that no issues arise from this fact. If for
any reason underflow occurs (AHB FIFO empty rises), you must perform the START
PROCEDURE.
• Initial configuration
— Write 8’h00 to ADDR_AUD_N3
— Write 8’h00 to ADDR_AUD_N2
— Write 8’h00 to ADDR_AUD_N1
— Write to ADDR_AUD_CTS3
— Write to ADDR_AUD_CTS3
— Write to ADDR_AUD_CTS2
— Write to ADDR_AUD_CTS1
• START PROCEDURE
— Write 8’h00 to ADDR_AUD_N3
— Write 8’h00 to ADDR_AUD_N2
— Write 8’h00 to ADDR_AUD_N1 (starts new DMA operation set the AHB_DMA START
bit)
— Wait for FIFO full
— Program N write to ADDR_AUD_N3
ERR005174
HDMI: HDMI AHB Audio DMA stream misalignment on system
initialization
