ERR007926
Chip Errata for the i.MX 6Dual/6Quad and i.MX 6DualPlus/6QuadPlus, Rev. 6.1, 06/2016
NXP Semiconductors
183
2. Choose the “SD/SDXC Speed” SDR12/SDR25 fuse configuration instead of SDR50/SDR104
when booting from an SD 3.0 card. SDR12/SDR25 is the default configuration. See i.MX6
device reference manual Fuse Map chapter for details on these fuses. If SD Card operation at
a higher speed is desired, the SD/MMC can be reconfigured after ROM boot. Note that these
fuses are also affected by ERR005645.
3. Boot from SPI-NOR initially then switch to SD/MMC
,
or One NAND once the external 32 kHz
clock is stable.
4. Extend the assertion of POR_B until the 32 kHz crystal oscillator is running and stable.
5. Provide an external stable 32 kHz clock input prior to de-assertion of POR_B.
OneNAND boot:
1. OneNAND: Choose a OneNAND memory with tRD1 less than 1.5 ms.
2. Boot from SPI-NOR initially then switch to SD/MMC
,
or One NAND once the external 32 kHz
clock is stable.
3. Extend the assertion of POR_B until the 32 kHz crystal oscillator is running and stable.
4. Provide an external stable 32 kHz clock input prior to de-assertion of POR_B.
NAND boot:
1. NAND: Choose a NAND memory with tRST less than 11 ms and tR less than 1 ms. Blow the
i.MX6 “Reset Time” fuse if the NAND device tRST is less than 6 ms. See i.MX6 device
reference manual Fuse Map chapter for details on this fuse.
2. Boot from SPI-NOR initially then switch to SD/MMC, NAND or One NAND once the external
32 kHz clock is stable.
3. Extend the assertion of POR_B until the 32 kHz crystal oscillator is running and stable.
4. Provide an external stable 32 kHz clock input prior to de-assertion of POR_B.
Proposed Solution:
No fix scheduled
Linux BSP Status:
Workaround possible but not implemented in the BSP, impacting functionality as described above.
