ERR005199
Chip Errata for the i.MX 6Dual/6Quad and i.MX 6DualPlus/6QuadPlus, Rev. 6.1, 06/2016
NXP Semiconductors
63
Description:
The PL310 Store Buffer does not have any automatic draining mechanism. Any written data might
consequently remain in this buffer, invisible to the rest of the system. In case an L3 external agent
keeps on polling this memory location, waiting to see the update of the written data to make any
further progress, then a system livelock might happen.
Conditions:
The erratum can only happen on Normal Memory regions. The following scenario is an example
which can exhibit the erratum, where an L3 agent might loop infinitely waiting for the notification
from CPU for an unbounded amount of time:
• An L3 agent is waiting for notification from CPU before making progress.
• CPU attached to PL310 issues such notification via a write access, which stays in PL310 store
buffer.
• No additional activity forcing the store buffer to drain is received by PL310.
Projected Impact:
Due to the erratum, a livelock situation might be encountered in the system.
Workarounds:
If a write access needs to be made visible to an L3 external agent, the workaround for this erratum
consists of using a Cache Sync operation in order to force the PL310 Store Buffer to drain. This is
illustrated in the following pseudo-code sequence:
STR // to be made visible to L3 DSB CACHE_SYNC.
In r3p2, a counter is implemented so that slots are automatically drained after 256 cycles of
presence in the store buffer. The i.MX 6Dual/6Quad has PL310-BU-00000-r3p1-50rel0.
Proposed Solution:
No fix scheduled
Linux BSP Status:
Software workaround integrated in Linux BSP codebase starting in release imx_3.0.35_4.1.0.
ERR005199
ARM/MP: 769419—No automatic Store Buffer drain, visibility of
written data requires an explicit Cache Sync operation [i.MX
6Dual/6Quad Only]
