ERR004308
Chip Errata for the i.MX 6Dual/6Quad and i.MX 6DualPlus/6QuadPlus, Rev. 6.1, 06/2016
116
NXP Semiconductors
Description:
Each time one writes to some FC registers, and depending on the clock relation of sfr clk and tmds
clk, some of these train of pulses (when these registers are configured in sequence), might not be
caught by the arithmetic unit while it is busy processing/updating the first ones, so, it gets wrong
video timing values, although the registers FC_* hold correct values. Even a soft reset will not
make the arithmetic unit update correctly. Video will still pass correctly to the HDMI, but packets
would not because the frame composer is holding internally incorrect video timing and this will
quickly build up and overflow the packet FIFOs.
Projected Impact:
Overflow of the packet FIFOs.
Workarounds:
Solution is, after all controller configuration has been done, write three-four times the same value
to any of the above registers (say FC_INVIDCONF with the correct same value three-four times),
and then perform soft reset to clock domains.
Proposed Solution:
No fix scheduled
Linux BSP Status:
Workaround possible but not implemented in the BSP, impacting functionality as described above.
ERR004308
HDMI: 8000504668—The arithmetic unit may get wrong video timing
values although the FC_* registers hold correct values
