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ERR005778
Chip Errata for the i.MX 6Dual/6Quad and i.MX 6DualPlus/6QuadPlus, Rev. 6.1, 06/2016
NXP Semiconductors
139
Description:
The measure unit counts cycles of an internal ring oscillator. The measure unit readout is used to
fine tune the delay lines for temperature/voltage changes for both DDR3 and LPDDR2 interfaces.
When operating at low frequencies (below 100 MHz), the measure unit counter might overflow
due to an issue in the overflow protection logic. As a result, an incorrect measure value will be read.
Projected Impact:
This might cause a rare issue if the measure unit counter stops within a small range of values that
translate to a delay that tunes the system incorrectly. This issue might not manifest in the
application because it is dependent on a combination of DDR frequencies coupled with specific
Process, Voltage, and Temperature conditions.
Workarounds:
To workaround this issue, following steps should be performed by software:
1. Prior to reducing the DDR frequency (528 MHz), read the measure unit count bits
(MU_UNIT_DEL_NUM).
2. Bypass the automatic measure unit when below 100 MHz, by setting the measure unit bypass
enable bit (MU_BYP_EN).
3. Double the measure unit count value read in step 1 and program it in the measure unit bypass
bit (MU_BYP_VAL) of the MMDC PHY Measure Unit Register, for the reduced frequency
operation below 100 MHz.
Software should re-enable the measure unit when operating at the higher frequencies, by clearing
the measure unit bypass enable bit (MU_BYP_EN). This code should be executed out of Internal
RAM or a non-DDR based external memory.
Proposed Solution:
No fix scheduled
Linux BSP Status:
Software workaround integrated in Linux BSP codebase starting in release imx_3.0.35_4.1.0.
ERR005778
MMDC: DDR Controller’s measure unit may return an incorrect value
when operating below 100 MHz