ERR003743
Chip Errata for the i.MX 6Dual/6Quad and i.MX 6DualPlus/6QuadPlus, Rev. 6.1, 06/2016
NXP Semiconductors
49
Description:
In the ARM L2 cache controller, PL310, hazard checking is done on bits [31:5] of the address.
When a read with Normal Memory (cacheable or not) attributes is received by PL310, hazard
checking is performed with the active writes of the store buffer. If an address matching is detected,
the read is stalled till the write completes.
Due to this erratum, a continuous flow of writes can stall a read targeting the same memory area.
Conditions:
The erratum occurs when the following conditions are met:
• PL310 receives a continuous write traffic targeting the same address marked with Normal
Memory attributes
• While treating this flow, PL310 receives a read targeting the same 32-byte memory area
Projected Impact:
When the conditions above are met, the read might be stalled till the write flow stops.
Note that this erratum does not lead to any data corruption.
Note also that normal software code is not expected to contain long write sequence like the one
causing this erratum to occur.
Workarounds:
There is no workaround for this erratum. A workaround is not expected to be necessary for this
erratum either.
Proposed Solution:
No fix scheduled
Linux BSP Status:
Software workaround not implemented in Linux BSP. Functionality or mode of operation in which
the erratum may manifest itself is not used.
ERR003743
ARM/PL310: 754670—A continuous write flow can stall a read
targeting the same memory area
