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ERR009605

Chip Errata for the i.MX 6Dual/6Quad and i.MX 6DualPlus/6QuadPlus, Rev. 6.1, 06/2016

NXP Semiconductors

- bit [23] – Disable Read-Allocate mode
- bit [22] – Disable Write Allocate Wait mode

Proposed Solution:

No fix scheduled

Linux BSP Status:

Software workaround implemented in Linux BSP codebase starting in release
imx_3.10.53_1.1.0_ga.

Summary of Contents for i.MX 6Dual

Page 1: ...detailed description in this document To identify the silicon revision refer to the last letter of the part number See Table 1 for examples For additional information see either the i MX 6Dual 6Quad A...

Page 2: ...by an erratum We have made our best attempt at providing software workaround requirements and BSP status for each erratum in this document Whether a software workaround has been implemented in the BSP...

Page 3: ...ERR009678 ERR009704 ERR009742 ERR009743 ERR009858 Updated the following i MX 6Dual 6Quad and i MX 6DualPlus 6QuadPlus specific errata ERR004366 Added Table 4 describing ARM errata not documented in th...

Page 4: ...following errata ERR006282 ERR006308 ERR006358 ERR006687 Updated the following ERR004353 ERR004446 ERR005829 Rev 1 1 2 2013 Restored pages omitted in Rev 1 Rev 1 1 2013 Added the following ERR006223...

Page 5: ...s addresses are not mapped on Debug APB interface No fix scheduled 29 ERR003727 ARM 729818 In debug state next instruction is stalled when sdabort flag is set instead of being discarded No fix schedul...

Page 6: ...le reads to aborting memory region clear the internal exclusive monitor may lead to livelock No fix scheduled 57 ERR005187 ARM MP 771223 Parity errors on BTAC and GHB are reported on PARITYFAIL 7 6 re...

Page 7: ...n data banking is implemented data parity errors can be incorrectly generated No fix scheduled 84 CAAM ERR004320 CAAM Three encryption functions may show up as available even though they are not No fi...

Page 8: ...AN FlexCAN does not transmit a message that is enabled to be transmitted in a specific moment during the arbitration process No fix scheduled 106 GPMI ERR008001 GPMI GPMI does not support the Set Feat...

Page 9: ...127 MIPI ERR004310 MIPI Glitch or unknown clock frequency on MIPI input clock may occur in case the CCM source clock is modified No fix scheduled 128 ERR005190 MIPI CSI2 Data lanes are activated befo...

Page 10: ...ZE No fix scheduled 146 ERR003755 PCIe 9000402443 Uncorrectable Internal Error Severity register bit has incorrect default value No fix scheduled 147 ERR003756 PCIe 9000387484 LTSSM Software initiated...

Page 11: ...fix scheduled 170 ERR007556 PCIe Core Delays Transition From L0 To Recovery After Receiving Two TS OS And Erroneous Data 9000597455 No fix scheduled 171 ERR007557 PCIe Extra FTS sent when Extended Sy...

Page 12: ...coming data FIS No fix scheduled 195 ERR003764 SATA 9000447882 ERR_I bit set when PhyRdy goes low during non data FIS reception No fix scheduled 196 ERR003765 SATA 9000447627 Global reset does not cle...

Page 13: ...ut error in Device mode No fix scheduled 216 uSDHC ERR004364 uSDHC Limitations on uSDHC3 and uSDHC4 clock gating No fix scheduled 217 ERR004536 uSDHC ADMA Length Mismatch Error may occur for longer re...

Page 14: ...rations i MX6 does not implement parity hence errata not applicable The parity feature is disabled by default and should not be enabled 761321 MRC and MCR are not counted in event 0x68 i MX6 does not...

Page 15: ...en though the VDDARM_IN supply is already stable the VDDARM_CAP supply will take about 2 ms to rise to the correct voltage Projected Impact ARM core might fail to resume Workarounds The software worka...

Page 16: ...set it to a higher value 4 Write the ICCEOIR End of Interrupt register Under these conditions due to the erratum the Global Timer might generate a second spurious interrupt request to the processor at...

Page 17: ...ot needed in the BSP Functionality or mode of operation in which the erratum may manifest itself is not used The BSP does not use ARM global timer The configuration and logic of the kernel does not ma...

Page 18: ...quence might trigger the erratum STR A STR A STR A STR B STR A or STR B At the time where the first four STR are in the Cortex A9 store buffer and the fifth STR arrives at a very precise cycle in the...

Page 19: ...hen this bit is set the fast lookup optimization in the Store Buffer is disabled which will prevent the failure to happen Setting this bit has no visible impact on the overall performance or power con...

Page 20: ...ting for an overflow to occur then polling can be used to detect when an overflow event has been missed An overflow can be determined to have been missed if the unsigned value in the counter is less t...

Page 21: ...6Dual 6Quad and i MX 6DualPlus 6QuadPlus Rev 6 1 06 2016 NXP Semiconductors 21 support for this profiling feature as required but should ensure the multiple errata impacting the ARM PMU are considere...

Page 22: ...essors in the MPCore cluster If the other processors in the cluster receive this second maintenance operation before having completed the first ICIALLUIS operation then the erratum occurs as the other...

Page 23: ...Errata for the i MX 6Dual 6Quad and i MX 6DualPlus 6QuadPlus Rev 6 1 06 2016 NXP Semiconductors 23 Linux BSP Status Software workaround implemented in Linux BSP codebase UBOOT starting in release imx...

Page 24: ...the processor is in SMP mode ACTLR SMP 1 b1 Projected Impact When the bug happens a data corruption or a processor deadlock can happen Workarounds The workaround for this erratum requires not enabling...

Page 25: ...This implies that the unaligned access must hit in the micro TLB for the first part of its request Projected Impact A valid watchpoint trigger is missed Workarounds In case a watchpoint is set on any...

Page 26: ...ted Note that there is no Trustzone Security risk because the Security state of the access is held in the microTLB and cannot be corrupted Projected Impact The errata might cause MMU translation corru...

Page 27: ...ew value ISB Change Translation Table Base Register to new value and the sequence Set TTBCR PD0 1 ISB Change ASID to new value Change Translation Table Base Register to new value ISB Set TTBCR PD0 0 b...

Page 28: ...EVENT bits to toggle in case an ISB is executed PMUEVENT 13 relates to event 0x0C PMUEVENT 14 relates to event 0x0D Workarounds Count ISB instructions along with event 0x90 The user should subtract th...

Page 29: ...is compliant with the ARM Debug architecture So the erratum only applies to the alias addresses through the external Debug APB interface Projected Impact If the debugger or any other external agent tr...

Page 30: ...a loss of performance when debugging Do not use stall mode Do not use stall mode when doing load store operations Always check for a sticky abort after issuing a load store operation in stall mode th...

Page 31: ...Impact The implication of this erratum is that Neon instructions cannot be counted reliably in the versions of the product that are affected by this erratum Workarounds No workaround is possible to ac...

Page 32: ...uted is causing some stalls in the processor pipeline Under certain timing conditions specific to the Cortex A9 micro architecture a cycle stall in the processor pipeline might hide the instructions m...

Page 33: ...are workaround is not needed because this erratum will never be encountered in normal device operation The Freescale Linux BSP does not support this optional profiling feature Users may add support fo...

Page 34: ...for another resource for example instruction side or because the PLD request itself to the mainTLB is missing and causing a Page Table Walk Also note that the above conditions are not sufficient to r...

Page 35: ...fix scheduled Linux BSP Status Software workaround not needed in the BSP Functionality or mode of operation in which the erratum may manifest itself is not used Users should check their custom OS and...

Page 36: ...jected Impact In case the non explicit memory request receives an external imprecise abort response while the processor is ready to enter into WFI state the processor might cause a deadlock In practic...

Page 37: ...with no offset DBGPCSR 1 0 contains the execution state of the target branch instruction 0xb00 for an ARM state instruction 0xb01 for a Thumb2 state instruction 0xb10 for a Jazelle state instruction...

Page 38: ...Solution No fix scheduled Linux BSP Status Software workaround is not needed because this erratum will never be encountered in normal device operation Software workaround not applicable to the BSP sin...

Page 39: ...Workarounds The workaround for this erratum can be not to use conditional LDREX along with non conditional STREX If no conditional LDREX is used the erratum cannot be triggered If conditional LDREX i...

Page 40: ...rt might be reported to the core when it should not In practice the failure is not expected to cause any significant issues to the system because imprecise aborts are usually unrecoverable failures Be...

Page 41: ...s on incrementing a counter writing the same word at the same address The external agent possibly another processor is polling on this address waiting for any update of the counter value to proceed Th...

Page 42: ...r the ARM Linux kernel common code has added the necessary DMB in places to ensure the visibility of the written data to any external agent The workaround for this erratum is to insert a DMB operation...

Page 43: ...GDSCR cannot be cleared by the external debugger In practice this makes the Sticky Pipeline Advance bit concept unusable on Cortex A9 processors Workarounds There is no practical workaround for this e...

Page 44: ...ot supposed to be generated by any compiler nor used by any handcrafted program Workarounds A possible workaround for this erratum is to modify the instruction encoding with bits 15 12 4 b1111 so that...

Page 45: ...ratum a corrupted line may be evicted or transferred from the processor without the parity error being detected and reported Workarounds There is no workaround for this erratum Proposed Solution No fi...

Page 46: ...ork with Data Cache enabled and access some cacheable memory regions Write Back either Shared or Non Shared The memory system underneath the processor needs to be able to generate aborts in this memor...

Page 47: ...to this erratum such an eviction request can be missed leading to the loss of dirty data in the L2 cache Conditions This problem occurs when the following conditions are met The double linefill featur...

Page 48: ...in the master interface Projected Impact When the above conditions are met the linefill resulting from the L2 cache miss is not issued till the flow of SO Device reads stops Note that each PL310 maste...

Page 49: ...ic targeting the same address marked with Normal Memory attributes While treating this flow PL310 receives a read targeting the same 32 byte memory area Projected Impact When the conditions above are...

Page 50: ...of code which rely on this read ordering behavior A first workaround for this erratum consists in using LDREX instead of standard LDR in volatile memory places where a strict read ordering is required...

Page 51: ...and invalidate data or unified cache line by MVA to PoC The erratum might arise when the second CPU is performing either of A read request resulting from any Load instruction the Load can be a specula...

Page 52: ...ster located at offset 0x30 from the PERIPHBASE address Setting this bit disables the migratory bit feature This forces a dirty cache line to be evicted to the lower memory subsystem which is both the...

Page 53: ...he rate of MRC and MCR instructions in the code Workarounds No workaround is possible to achieve the required functionality of counting how many instructions are precisely passing through the register...

Page 54: ...ed systems because these accesses are mainly intended to be used as part of debug over power down sequences which is not a feature supported by the Cortex A9 Workarounds The workaround for this erratu...

Page 55: ...where a system is impacted by this erratum a software workaround is available which consists in setting bit 20 in the undocumented Control register which is placed in CP15 c15 0 c0 1 This bit needs to...

Page 56: ...ecuted A serial branch is one of the following Data processing to PC with the S bit set for example MOVS pc r14 LDM pc Projected Impact Due to the erratum the trace flow might not start or stop as exp...

Page 57: ...cted so the LDR afterwards is speculatively executed So the processor keeps on executing LDR to aborting region this speculative LDR now appears before the LDREX and DSB LDREX DSB STREX The LDR misses...

Page 58: ...appen and cause timing changes which might exit the processor from its livelock situation Branch prediction is very usually enabled so the final branch in the loop will usually be correctly predicted...

Page 59: ...ight cause a branch mispredict but no functional failure In systems which are implementing parity error detection on the BTAC and GHB RAMs the erratum is not expected to cause any significant issue be...

Page 60: ...ratum the eviction buffer can incorrectly sample error information As a result an eviction can be wrongly cancelled and dirty data can be lost leading to data corruption Note that data parity error is...

Page 61: ...low this erratum does not apply as far as TAGERR is concerned In a system using TAGERR for indicating Tag RAM error the eviction buffer can only sample a true error coming from the Tag RAM However th...

Page 62: ...ality or mode of operation in which the erratum may manifest itself is not used The erratum only affects configurations which implement the parity support option i MX6 parity is not supported In the F...

Page 63: ...such notification via a write access which stays in PL310 store buffer No additional activity forcing the store buffer to drain is received by PL310 Projected Impact Due to the erratum a livelock sit...

Page 64: ...1 One of the Prefetch Enable bits bits 29 28 of the Auxiliary or Prefetch Control Register is set HIGH 2 The prefetch offset bits are programmed with value 23 5 b10111 Projected Impact When the condi...

Page 65: ...een exception returns of the form LDM PC with base address register write back and the total number of exceptions returns Workarounds There is no workaround to this erratum Proposed Solution No fix sc...

Page 66: ...ition Any other kind of code can be executed here starting with the abort exception handler following the aborted cache maintenance operation An ISB instruction is executed by the processor No memory...

Page 67: ...ect because either a The conditional Load Exclusive or Store Exclusive instruction failed its condition code check b The conditional branch was mispredicted so that all subsequent instructions specula...

Page 68: ...P Functionality or mode of operation in which the erratum may manifest itself is not used There are some cases where Linux ends up with Strongly Ordered memory MT_UNCACHED or pgprot_noncached Freescal...

Page 69: ...physical page The OS might have an existing mapping to a physical page the old mapping but wants to move the mapping to a new page the new mapping To do this the OS might 1 Write a new translation ent...

Page 70: ...ave a noticeable performance penalty Note that inserting a DSB instruction immediately after writing the new translation table entry significantly reduces the probability of hitting the erratum but it...

Page 71: ...he write instruction to Strongly Ordered memory region receives its acknowledge BRESP response on AXI while the LDREX is being executed the erratum can happen Projected Impact The erratum leads to a f...

Page 72: ...functions will be used A free running JTAG_TCK can also be used Proposed Solution No fix scheduled Linux BSP Status Software workaround not implemented in Linux BSP Functionality or mode of operation...

Page 73: ...xecuting the short loop from executing the received broadcast CP15 operation As a result the processor that originally executed the broadcast CP15 operation is stalled until the execution of the loop...

Page 74: ...ses the deadlock For example Inserting a nonconditional Load or Store instruction in the loop between each DMB Inserting additional instructions in the loop such as NOPs to prevent the processor from...

Page 75: ...can occur only if the following sequence of conditions is met 1 MMU and branch prediction are enabled 2 Branches are executed 3 MMU is disabled and branch prediction remains enabled Projected Impact I...

Page 76: ...cheable or Cacheable Write Through 3 The write request is targeting a memory region marked as Normal Memory Cacheable Write Back and Shareable and the CPU is in AMP mode Projected Impact This erratum...

Page 77: ...e communication variable DMB ensure the previous STR is complete Also any IRQ or FIQ handler must execute a DMB at the start to ensure the clearing of any communication variable is complete 2 Ensure t...

Page 78: ...gested write traffic The other coherent agent either another CPU in the cluster or the ACP must perform its coherency request on the evicted line while it is in the eviction buffer This erratum only o...

Page 79: ...ip Errata for the i MX 6Dual 6Quad and i MX 6DualPlus 6QuadPlus Rev 6 1 06 2016 NXP Semiconductors 79 Linux BSP Status Software workaround implemented in Linux BSP codebase starting in release imx_3 1...

Page 80: ...tant to note that any scenario leading to this deadlock situation is uncommon It requires two or more processors writing full cache lines to a coherent memory region without taking any semaphore with...

Page 81: ...QuadPlus Rev 6 1 06 2016 NXP Semiconductors 81 bit 23 Disable Read Allocate mode bit 22 Disable Write Allocate Wait mode Proposed Solution No fix scheduled Linux BSP Status Software workaround impleme...

Page 82: ...in condition 1 b The Write Context ID event is mapped to this selected PMU by setting PMXEVTYPER evtCount to 0x0B 3 The PMU is enabled by setting the PMCR E bit to 1 4 A read access occurs to the CON...

Page 83: ...ssor is in reset state DBGPRSR SR might be set to 1 when it should not when the debug logic of the processor is in reset state In both cases the DBGPRSR SR bit value might be corrupted which might pre...

Page 84: ...t registers where no actual error exists Projected Impact Because of this erratum false data parity errors might be reported by the PL310 Level 2 Cache Controller and can cause system instability Work...

Page 85: ...f crypto operation When this fuse is blown this register should show that there are 0 of each encryption accelerator However it actually shows that 1 is available Projected Impact The three encryption...

Page 86: ...age it into a blob The issue found is that CAAM logs a read access error into a status register when it decapsulates a blob and writes the contents to the protected key partition This logging of the r...

Page 87: ...ead write from to the RAM Workarounds The Internal 16 Kb RAM accesses CAAM should not be cached Users should ensure that the MMU table does not have this 16 Kb region mapped as cacheable memory region...

Page 88: ...ng multiple AXI read transactions with different AXI IDs The workarounds are as follows Workaround 1 The first workaround is to only issue a single descriptor to CAAM at a time CAAM will not pre fetch...

Page 89: ...he PGC unit is in the middle of the power down sequence The counter needs to be set cleared only when there are no interrupts pending The counter needs to be enabled as close to the WFI Wait For Inter...

Page 90: ...1 0 is set to 2 b01 or STOP mode if CCM_CLPCR 1 0 is set to 2 b10 Projected Impact This issue can lead to errors ranging from module underrun errors to system hangs depending on the specific use case...

Page 91: ...LDB_DIx_IPU clock under certain conditions Projected Impact Switching LDB clock sources on an asynchronous clock multiplexer without gating the input and output clock can cause clock glitches to propa...

Page 92: ...he i MX 6Dual 6Quad and i MX 6DualPlus 6QuadPlus Rev 6 1 06 2016 92 NXPSemiconductors Proposed Solution No fix scheduled Linux BSP Status Software workaround integrated in Linux BSP codebase starting...

Page 93: ...ing DMA to transfer data to the eCSPI TXFIFO Workarounds This errata is only seen when the SMC Start Mode Control bit is set A modified SDMA script with TX_THRESHOLD 0 and using only the XCH SPI Excha...

Page 94: ...negation of SSB always causes completion of the burst However due to the above issue the data is not sampled correctly in RxFIFO when BURST_LENGTH 1 mod32 is not equal to actual burst length mod32 The...

Page 95: ...ENGTH 0x020 the ECSPI will transmit the first bit of word 0 followed by the entire word 0 then transmit the data as expected The transmitted sequence in this example will be 0 0x00000001 1 0x00000001...

Page 96: ...32 MB there is no impact This mode is related to a unique memory configuration that is not often used Most systems can work in the default mode AUS 0 Board designers should connect the EIM address bus...

Page 97: ...be tested as input only Workarounds Because the signals listed above cannot be driven as outputs interconnect tests on these signals can only be performed if the external devices connected to these p...

Page 98: ...hroughput to around 400 Mbps ENET remains fully compatible to 1Gb standard in terms of protocol and physical signaling If the TX and RX peak data rate is higher than 400 Mbps there is a risk of ENET R...

Page 99: ...aside from the frame drops Workarounds The application might want to implement some flow control to ensure the line rate burst traffic is below 400 Mbps if it only uses consecutive small frames with m...

Page 100: ...the Timer Compare Capture Register ENET_TCCRn Due to an integration issue the ENET 1588 clock and Channel 2 event capture compare signal are both connected to the same GPIO16 pin Projected Impact ENET...

Page 101: ...transition on ENET_TDAR TDAR Projected Impact Reduced ENET performance due to delayed servicing of interrupts Workarounds Code can use the transmit frame interrupt flag ENET_EIR TXF as a method to de...

Page 102: ...performance of the ENET block because its interrupts are serviced only when the chip exits Wait mode due to an interrupt from some other wake up source Projected Impact Reduced ENET performance due to...

Page 103: ...d Impact Underrun overrun may cause audio channel swap Workarounds Underrun overrun in the ESAI should be prevented at the system level If channel swap occurs the ESAI must be reset according to the r...

Page 104: ...at exclusive writes are always successful Projected Impact EIM does not support exclusive accesses according to AXI specifications Workarounds Use DDR or OCRAM memories when performing exclusive acces...

Page 105: ...the EIM region through Trustzone is not supported Workarounds To prevent unpredictable behavior prior to accessing the EIM region set all bits in the EIM CSU_CSL field to 1 so that all accesses are a...

Page 106: ...ge buffer 13 to be scanned by arbitration process In this case it does not detect the new code 0xC and no new arbitration is scheduled The problem can be detected only if the message traffic ceases an...

Page 107: ...bytes 5 Write the DLC Control and CODE fields of the Control Status word to activate the message buffer 6 The workaround consists of executing two extra steps 7 Reserve the first valid mailbox as an i...

Page 108: ...o use the NANDF_DQS signal to write data to the Toggle NAND flash So the Set Feature command in Toggle mode is not supported Projected Impact The Set Feature command cannot be used in Toggle mode Work...

Page 109: ...n the system Projected Impact Deadlock in the system Workarounds GPU2D should not be mistakenly accessed by software when power gated Proposed Solution No fix scheduled Linux BSP Status Software worka...

Page 110: ...as the software rendered image Workarounds There are no software workarounds that completely resolve the issue The filter blit API can be used instead of the stretch blit for BLIT acceleration however...

Page 111: ...equests doubling the number of requests processed internally in L1 cache Projected Impact Application performance is reduced when L1 cache is present and data requests are unaligned to 16 bytes Workar...

Page 112: ...cache line When either of these conditions happens the last 8 bytes of data are paired with the address of the subsequent cache line and the entire cache line gets written to the wrong location The l...

Page 113: ...ater than 8 million pixels and consequently the Texture Engine might sample black texels Projected Impact Visual impact will vary depending on whether the application texture is clamped or wrapped Wor...

Page 114: ...HB Audio DMA does not generate the intdone bit interrupt although it stops requesting transactions Conditions Setup the system memory with low bandwidth audio audio sampling rate 32 kHz two active cha...

Page 115: ...nspecified length burst INCR however it is not recommended to use INCR in i MX 6Dual 6Quad due to poor bus performance PL301 convert AHB INCR to AXI SINGLE transfers This issue can be ignored Workarou...

Page 116: ...will still pass correctly to the HDMI but packets would not because the frame composer is holding internally incorrect video timing and this will quickly build up and overflow the packet FIFOs Project...

Page 117: ...e the AHB audio DMA done interrupt Projected Impact HDMI will not generate the AHB audio DMA done interrupt if the DMA burst read transaction address region is greater than 8 KB Workarounds The Config...

Page 118: ...nspecified INCR instruction only other types of INCR forbidden For multi channel 4 6 or 8 channels and the whole range of sample rates supported from 32k to 192k the workaround consists in setting a t...

Page 119: ...e remote HDCP Features 1 1 support has been indicated on the I2S BCAPS register Projected Impact HDCP might transmit incorrect Ainfo value causing a failure on the receiver side A failure can only occ...

Page 120: ...a 10 0 istart regupdatearithunit 1 oquotient wi01quotient 4 0 orest wi01rest 9 0 odone wi01done RSR COMMENT restofpacketsonhblankwextctrl Hblank extctrlperiod LDGB numseqonhblank ctrlperiod LDGB datap...

Page 121: ...rectly and cause packet queue overflow Projected Impact Audio packet FIFO overflow It will generate audio noise or no audio output Workarounds The programming flow should be 1 Program all the controll...

Page 122: ...e with no knowledge of the DWC_hdmi_tx enabled system Workarounds This procedure assumes that all of the buffers provided to the AHB audio DMA through the AHB_DMA_STRADDR and AHB_DMA_STPADDR registers...

Page 123: ...1 06 2016 NXP Semiconductors 123 Write to ADDR_AUD_N2 Write to ADDR_AUD_N1 Proposed Solution No fix scheduled Linux BSP Status Software workaround integrated in Linux BSP codebase starting in release...

Page 124: ...0x0012671F Note this issue only affects the registers associated with HDCP functions Other HDMI functions are not affected Projected Impact Invalid data will be read by the ARM core Workarounds For re...

Page 125: ...f the I2C specification for the SCL low period Workarounds In order to exactly meet the clock low period requirement at fast speed mode SCL must be configured to 384 KHz or less The following clock co...

Page 126: ...faces to DDR input mode might not work Conditions De assertion of POR_B when the SoC is powered up Projected Impact DDR3 LPDDR2 MIPI_HSI USB_HSIC and ENET I O interfaces might not work together Workar...

Page 127: ...e of the particular pixel formats from 32 pixels to 16 pixels If the IDMAC bandwidth is enough there s no impact on the capture performance it s just a system bandwidth consumption increase due to low...

Page 128: ...in CCM Projected Impact Glitch or unknown clock frequency on MIPI pixel clock can lead to unknown behavior Workarounds Apply software reset to MIPI in case the aclk_emi_podf or aclk_emi_sel in the CCM...

Page 129: ...e Projected Impact Affects the non active data lanes status register value and adds some minor power consumption 1 2 mA however there will not be any packet loss Once the HS clock is detected the data...

Page 130: ...the size protection is applied without considering that this field now contains data and not packet size Short packet commands are erroneously transmitted in DSI link with WC field equal to 16 hFFEE w...

Page 131: ...register ERROR_ST1 Projected Impact The CRC error is asserted in the bit crc_err of the register ERROR_ST1 when DSI received a long packet with no payload This errata does not affect the correct func...

Page 132: ...splay or fail the command send Workarounds Setting PWR_UP register address 0x04 to 0x00 keeps the controller under reset so that en_video_mode and en_cmd_mode can be changed free of any timing violati...

Page 133: ...with next line transmission resulting in the corruption of the packets Projected Impact It will lead to the overlapping of two adjacent lines display data Workarounds This problem only occurs when an...

Page 134: ...lanking packet under these conditions can only be observed in Video Synchronous Mode with pulses Projected Impact Incorrect video stream in some conditions Workarounds HSA and HBP should be programmed...

Page 135: ...ly generated error interrupt Workarounds To avoid the interrupt err_id can be masked by setting the bits 12 to 15 of the MASK2 register Bits 12 to 15 of the ERR2 register also should be ignored when r...

Page 136: ...uld match what is described in the databook and dvalid should not be activated by Null and Blanking data Projected Impact None Workarounds The dvalid signal can be filtered by configuring the followin...

Page 137: ...nes 2 Vertical blanking before the frame end FE is 0x40000 CSI_CLK0 period 3 No line start and line end short packets occur during the frame The functionality of the receive data is not impacted only...

Page 138: ...sub buffer mode The user should set the MFE bit to 0 in the Channel Allocation Table CAT in order to avoid this issue Proposed Solution No fix scheduled Linux BSP Status Software workaround not neede...

Page 139: ...fic Process Voltage and Temperature conditions Workarounds To workaround this issue following steps should be performed by software 1 Prior to reducing the DDR frequency 528 MHz read the measure unit...

Page 140: ...saction reordering only up to the default aging level 15 and assigns a highest priority tag to the outstanding transaction Projected Impact The aging scheme optimizes the transaction reordering only u...

Page 141: ...register The read data value returned to the requester is the hardwired default value 2 Issue a DBI read to same Port Logic Segmented Buffer Depth register The read data value returned to the requeste...

Page 142: ...s address check rule are dropped but no error is reported Conditions Issue an inbound memory TLP that has an address larger than the AMBA or RTRGT1 address bus width Projected Impact When the requirem...

Page 143: ...tatus bit in the same Status Register then the status bit corresponding to the MSI interrupt is set but the status bit being written by software is not cleared and remains set As a result even though...

Page 144: ...Requester ID in the PME Requester ID field corresponds to the second PM_PME and not the initial PM_PME received by the core Projected Impact The Requester ID of the initial PM_PME is lost and not cor...

Page 145: ...l overwrite the first completion timeout in the storage element This results in the information associated with the first timeout being lost and no response is returned on the AHB or AXI slave interfa...

Page 146: ...responds with UR status when it should respond with CA status Projected Impact Software gets the wrong status Workarounds None Proposed Solution No fix scheduled Linux BSP Status Software workaround...

Page 147: ...tional feature that the PCI Express block does not support but it must default to 1 b1 anyway Projected Impact If user chooses to implement Uncorrectable Error it is not supported and is not compliant...

Page 148: ...xpress block chooses to send Idle symbols as the specification does not prohibit the sending of Idle symbols Projected Impact The device that initiates the state transition moves from Recovery Idle th...

Page 149: ...example scenario for this erratum 1 Setup an inbound iATU region with the type field set to match messages and the vendor ID match mode bit set to 1 2 Send a message that matches the bits 47 ATU_REG_W...

Page 150: ...Projected Impact Upstream Port receives TS OSs and transitions to L2_IDLE state This causes Upstream Port to lose synchronization with Downstream Port This is not a problem for the Downstream Port be...

Page 151: ...interface 1 Setup any outbound iATU region any type any target address 2 Send a message using VMI where the lower 32 bits of the message match the iATU region 3 The resulting Vendor Message TLP will b...

Page 152: ...RTRGT0 interface The core correctly disregards the poisoned status as the CA response is a high priority error However the poisoned bit causes the internal filter to treat the request as UR instead of...

Page 153: ...oves ahead regardless of the non PAD lane number not being the same in two consecutive TS OS Projected Impact This violates PCIe Base Specification two consecutive TS Ordered Sets are received The cor...

Page 154: ...error during reception of the DLLP or if the DLLP ends with an ENDB symbol and not an END symbol These extra conditions should not result in the reporting of a bad DLLP error Projected Impact A bad D...

Page 155: ...e_State_Request_L1 TLPs Do not acknowledge the PM_Active_State_Request_L1 TLPs but bring the link down by forcing the remote partner into the detect state Allow the link to retrain to L0 After the lin...

Page 156: ...must retransmit 30 a TLP out of its Data Link Layer Retry buffer if required by the Data Link Layer rules In Addition For Entry into The L0s State 5 4 1 1 1 Entry into the L0s State No TLP is pending...

Page 157: ...is that L0S PCI Express Link Power State will be exited prematurely if this condition is hit however will re enter if the condition to enter prevails So just an early exit out of L0S but not functiona...

Page 158: ...this event as the receiver on the other side drops the re transmitted TLP as a duplicate TLP If the missed frame is a TLP no ACK will be sent to the link partner resulting in re transmission of the T...

Page 159: ...any compliance issues are encountered Projected Impact RX equalization cannot be modified Workarounds The workaround is to override the RX_EQ settings accordingly using control registers inside the P...

Page 160: ...at was inserted between the two TS1 Ordered Sets Projected Impact Consequences The core might miss the second TS1 OS Because the remote partner only sent two TS1 OSs the core will not receive a second...

Page 161: ...and i MX 6DualPlus 6QuadPlus Rev 6 1 06 2016 NXP Semiconductors 161 Linux BSP Status Software workaround cannot be implemented to mask or workaround this SoC issue This erratum will result in impacte...

Page 162: ...ning Conditions Scenario Setup 1 Transmit a series of TLPs from the core 2 Send a Nak DLLP for the first TLP to initiate a replay 3 Wait for the replay to begin 4 Send a Nak DLLP for the first TLP to...

Page 163: ...cy update inputs to CDR phase mixer Once the pointers are misaligned the condition will persist until the clocks are disabled or another phase shift occurs in clock phases as a result of rate change T...

Page 164: ...rx_valid is bit 0 MAC software registers 1 Disable enable LTSSM write app_ltssm_enable 2 Disable Gen2 read write link capability status register 3 Link in L0 event driver should know this when the dat...

Page 165: ...cvrCfg state core will send less than 32 TS2s before transition to Recovery Speed Projected Impact The speed change negotiation might fail Workarounds In current PCIe core there is no signal indicatin...

Page 166: ...back to core LTSSM misses the PhyStatus because core_clk is still gated off by the clk_rst module Projected Impact The core s LTSSM does not proceed to exit from Recovery and is awaiting a Powerdown...

Page 167: ...nt to adjust the Link speed autonomously Train the Link to Hot Reset Core will have a Link down reset which causes non sticky reset Projected Impact The component is permitted to autonomously adjust t...

Page 168: ...power and wake up only by the OOB Out of Band wakeup signal since wakeup by a beacon from link partner is not supported driven from the link partner End Point This signal could be used as a GPIO inter...

Page 169: ...s than the maximum number of MSI vectors are requested by the core Projected Impact Low This issue has no impact on the MSI functionality and only affects the PCI SIG compliance tests CFG 4 0 1 Workar...

Page 170: ...region rather than requiring multiple address translation tables or a 4GB translation space The BDF is then supposed to be shifted back up from bits 27 12 to 31 16 in the outgoing TLP actually Bytes...

Page 171: ...ous data Scenario Setup Linkup to L0 Send two TS ordered sets to the core Send some erroneous data to the core immediately Continue sending erroneous data to the core for 128 us Projected Impact Core...

Page 172: ...mode because the Extended Synch bit is used for external Link monitoring tools It is not used in an operational PCIe Link When the core transmits FTS the remote partner is in Rx_L0s FTS The next state...

Page 173: ...number Projected Impact This might confuse the remote partner and lead to the formation of a narrower link Workarounds None Proposed Solution No fix scheduled Linux BSP Status No software workaround...

Page 174: ...ce of link and lane number match checks in Recovery RcvrLock and Recovery RcvrCfg states only affects single lane configurations CX_NL 1 All configurations are not affect as stated in the Impacted Con...

Page 175: ...n setup and in a real system the remote partner must keep sending TS1s in Recovery RcvrLock and then core will move to Recovery after receiving 2 TS1s Projected Impact The core might miss the second T...

Page 176: ...nt as the receiver on the other side drops the re transmitted TLP as a duplicate TLP If the missed frame is a TLP no ACK will be sent to the link partner resulting in re transmission of the TLP from t...

Page 177: ...to executing a warm reset clear the IOMUXC_GPR1 REF_SSP_EN to disable the PCIe reference clock Once the warm reset is complete and the clocks are stable again re enable the PCIe reference clock by set...

Page 178: ...DO on with the GPU VPU clocks disabled consumes approximately 35 mW more than with the LDO off Workarounds If the PRE is in use the PU domain LDO must not be switched off To help reduce the power cons...

Page 179: ...dware write window For cases in which the PRE input line number is greater than 9 the software will read the STORE_BLOCK_Y status in the HW_PRE_STORE_ENGINE_STATUS register and verify it is within a s...

Page 180: ...issue For a hardware workaround implement an external watchdog or other reset watch such as via a PMIC On a successful boot the processor toggles the external watchdog through an I O mechanism for exa...

Page 181: ...the most significant 3 bits bits 7 6 5 of any parity bytes the Hamming Checking will fail The MSB 3 bits of parity byte should not be considered in the checking process So the ROM code may interpret a...

Page 182: ...se these modes do not use timeouts The potential effects are 1 The SD MMC card specification may be violated if the SD MMC card Nac parameter is larger than 50 ms or if its initialization time is grea...

Page 183: ...NAND Choose a OneNAND memory with tRD1 less than 1 5 ms 2 Boot from SPI NOR initially then switch to SD MMC or One NAND once the external 32 kHz clock is stable 3 Extend the assertion of POR_B until t...

Page 184: ...speed and continue normally with the boot process This mapping issue does not impact MMC boot Workarounds None The minimum SD clock speed supported is high speed mode SDR25 for initial booting in SD S...

Page 185: ...an endless loop Projected Impact The secondary boot might not work in the first attempt Workarounds There are no software workarounds for this issue instead the user will need to reboot the IC which...

Page 186: ...gh a relock cycle due to PLL reprogramming in rare circumstances the PFDs can enter into a similar unknown state It is therefore required that customer application software reset the respective PFDs u...

Page 187: ...the Linux BSP Status section Users without the ability to boot from SPI I2C or SATA fully or to load the patch should implement either an SPI I2C SATA Parallel NOR boot source or one of the other wor...

Page 188: ...ABLE eFuse to 1 This workaround applies for all boot sources except NAND boot either SLC or MLC For NAND boot the user must implement either the SPI I2C or SATA workaround or the external Watchdog wor...

Page 189: ...reset watch such as via a PMIC On a successful boot the processor toggles the external watchdog through some I O mechanism for example a GPIO which prevents the watchdog from firing If a boot failure...

Page 190: ...is called The problem occurs when the plug in calls this function again Projected Impact EIM NOR boot might fail if the workaround is not applied Workarounds There are two workarounds for this issue M...

Page 191: ...as been burned into NAND When the first block of the firmware area is bad and the NAND page size is 4K or lower this condition will occur A bad block which is not the first one in firmware area will n...

Page 192: ...the boot ROM being redirected to USB serial download mode Projected Impact System boot failure can be observed with SD card eMMC and NAND primary boot Workaround 1 Connect RTC_XTALI to an external 32...

Page 193: ...oes not meet the SATA specification Projected Impact Because an OOB receiver should look for three gaps four consecutive bursts this behavior should not affect normal operation It could prevent compli...

Page 194: ...d FIS area Projected Impact The FIS is unnecessarily delivered to the received FIS area However software does not normally examine the content of the received FISes so this behavior does not matter Th...

Page 195: ...eing cleared in P_Idle causing a transition to CFIS_SyncEscape2 while tx_sync_esc is asserted only in the CFIS_SyncEscape state Projected Impact The host does not generate a SYNC escape causing a lock...

Page 196: ...bits are set when Phy Not Ready condition is detected during a non data FIS From the software point of view this should not matter since it should use the P IS PRCS bit to recover from PhyRdy going l...

Page 197: ...Port module Projected Impact This erratum causes unnecessary interrupt processing The probability of this problem occurring is medium Workarounds Generate global reset when all P IS and IS bits are c...

Page 198: ...ases will assert both phy_partial and phy_slumber requests at the same time In other cases the core will assert just phy_slumber instead of phy_partial Both are incorrect behavior only phy_partial sho...

Page 199: ...mpletions multiple SACT bits are cleared and CCC is enabled if a subset of those multiple bits causes IS CCC 1 interrupt then the remaining bits are still counted as completions through hCccComplete r...

Page 200: ...as completed Projected Impact PRD intrq IS DPS 1 is asserted erroneously after the first TX Data FIS when it should not be asserted until after all the data in the PRD is transferred Because IS DPS 1...

Page 201: ...ycles instead of one This causes a tag FIFO coherency problem that can be fixed only by an asynchronous reset power up Projected Impact After reset completes and a D2H Register FIS is posted to memory...

Page 202: ...ing rx_firstdw and rx_dvalid for the FIS to the TCHK module after srst_req_asic 1 Projected Impact The SATA core does not respond to incoming traffic on the SATA bus Workarounds Use COMRESET if comman...

Page 203: ...e same time or the wrong mode is asserted In this case the PHY enters Slumber mode This only results in the PHY taking longer to wake up from power mode if clocks are turned off for Slumber and not fo...

Page 204: ...uses the Link state machine to move to sending SYNCs while waiting for SYNCs but because it is left IDLE the Device has already sent SYNCs and the Host should not check for them Projected Impact The S...

Page 205: ...fail to recognize the attached SATA device or may recognize that attached device but only be able to negotiate at the lower speed of 1 5 Gbps Workarounds Workaround 1 Turn off on the SATA_VPH power s...

Page 206: ...icable for devices that support this mode When power down is initiated from Slumber mode the PHY performs suspend resume correctly This workaround requires software modification Proposed Solution No f...

Page 207: ...used to return sense data for example Request Sense Inquiry Mode Sense 2 ATA streaming commands for example READ STREAM EXT READ STREAM DMA EXT Projected Impact When the read command completes and rea...

Page 208: ...uence of events occurs 1 Software issues a reset to the SNVS_LP logic by setting the HPCOMR 4 bit to 1 which is LP_SWR This clears the SNVS_LP registers and the bit returns to 0 2 Then the power to VD...

Page 209: ...during data transfer If the data register is accessed directly by software it should account for the shifted data and perform shifting to the right location Workarounds The data should be shifted to t...

Page 210: ...tion and identification of ignore_time_slot requires 4 ipg_clk cycles to fit in a half cycle of the external clock Projected Impact Data corruption in the specific configuration Workarounds Do not use...

Page 211: ...el mode Workarounds Use SSI in two channel mode TCH_EN 1 with two FIFOs enabled TFEN1 1 TFEN0 1 With two FIFOs in use left channel transmit data is from FIFO0 right channel transmit data is from FIFO1...

Page 212: ...too fast while the external device might still be in Full Speed mode the SOF signal level will be 800mV which will be recognized as a High Speed disconnection The USB controller may send the SOF pack...

Page 213: ...tection to signal power modes to a PMIC in an undercharged battery scenario where the standard USB current allotment is not sufficient to boot the system Workarounds Apply VDDHIGH_IN if battery charge...

Page 214: ...kets All other traffic is blocked Workarounds Set the host TXFIFO threshold to a large value TXFIFOTHRES in the TXFILLTUNING register This increases the tolerance to bus latency and avoids a FIFO unde...

Page 215: ...e PHY Low power suspend bit PHCD is cleared a USB interrupt USBSTS PCI will be generated In this case the PHCD bit will NOT be set because of the interrupt However if a remote wakeup occurs after the...

Page 216: ...ing current transactions to time out This situation will be recovered after FIFO is not overrun Projected Impact Implementing the workaround shown will prevent receive FIFO overruns but cause a 10 30...

Page 217: ...by usdhc4_clk_root CGR Projected Impact RAWNAND and APBHDMA clocks might be gated unintentionally Workarounds uSDHC3 and uSDHC4 clock gating controls should not be configured to gate the clocks in ca...

Page 218: ...from the card an incorrect block count is loaded by the DMA engine Projected Impact If the total latency of these AHB SINGLE bus accesses is longer than the latency of one block being read from the ca...

Page 219: ...irect mode and descriptor mode SPP sdma_ctrl block generates internal interrupt when switching from direct mode to descriptor mode The interrupt keeps high and this affects H 264 encoder H 264 encoder...

Page 220: ...annot find the start code and returns the SEQ_INIT error for decoding a Version 0 bitstream The VPU can decode a Version 1 bitstream Projected Impact Version 0 of Sorenson Spark bitstream cannot be de...

Page 221: ...tion Projected Impact VPU will not work Workarounds If the remaining bitstream in the bitstream buffer is less than 8 bytes then the application should fill 0 s until there are 8 bytes in the buffer T...

Page 222: ...ctor of neighborhood MB is not zero left or above The negated motion vectors in the left and above MBs are same Projected Impact Causes a macro block of P picture decoding error thus causes visual qua...

Page 223: ...should be written twice Projected Impact WDOG software reset request might be ignored Workarounds The WDOG SRS software reset bit should be written twice within one period of the 32 kHz clock Proposed...

Page 224: ...nce In some cases the oscillator may not start at all Workarounds The addition of a 2 2 M ohm external resistor from the XTALI pin to ground is required for all designs Proposed Solution No fix schedu...

Page 225: ...r specifications can and do vary in different applications and actual performance may vary over time All operating parameters including typicals must be validated for each customer application by cust...

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