ERR007008
Chip Errata for the i.MX 6Dual/6Quad and i.MX 6DualPlus/6QuadPlus, Rev. 6.1, 06/2016
76
NXP Semiconductors
Description:
Under certain timing circumstances specific to the Cortex-A9 microarchitecture, a write request to
an Uncacheable, Shareable, Normal memory region might be executed twice, causing the write
request to be sent twice on the AXI bus. This might happen when the write request is followed by
another write into the same naturally aligned doubleword memory region, without a DMB between
the two writes.
The repetition of the write usually has no impact on the overall behavior of the system, unless the
repeated write is used for synchronization purposes.
The erratum requires the following conditions:
• A write request is performed to an Uncacheable, Shareable, Normal memory region.
• Another write request is performed into the same naturally doubleword-aligned memory region.
This second write request must not be performed to the exact same bytes as the first store.
A write request to Normal memory region is treated as Uncacheable in the following cases:
1. The write request occurs while the data cache is disabled.
2. The write request is targeting a memory region marked as Normal Memory Non-Cacheable or
Cacheable Write-Through.
3. The write request is targeting a memory region marked as Normal Memory Cacheable
Write-Back and Shareable, and the CPU is in AMP mode.
Projected Impact:
This erratum might have implications in a multimaster system where control information is passed
between several processing elements in memory using a communication variable, for example a
semaphore. In such a system, it is common for communication variables to be claimed using a
Load-Exclusive/Store-Exclusive, but for the communication variable to be cleared using a
non-Exclusive store. This erratum means that the clearing of such a communication variable might
occur twice. This might lead to two masters apparently claiming a communication variable, and
therefore might cause data corruption to shared data.
Here is a scenario in which this might happen:
MOV r1,#0x40
; address is double-word aligned, mapped in normal noncacheable
shareable memory
Loop: LDREX r5, [r1,#0x0]
; read the communication variable
CMP r5, #0
; check if 0
STREXEQ r5, r0, [r1]
; attempt to store new value
CMPEQ r5, #0
; test if store succeeded
BNE Loop
; retry if not
DMB
; ensures that all subsequent accesses are observed when gaining
of the communication variable has been observed
; loads and stores in the critical region can now be performed
MOV r2,#0
MOV r0, #0
ERR007008
ARM/MP: 794074 --A write request to Uncacheable Shareable memory
region might be executed twice
