ERR003719
Chip Errata for the i.MX 6Dual/6Quad and i.MX 6DualPlus/6QuadPlus, Rev. 6.1, 06/2016
20
NXP Semiconductors
Description:
Overflow detection logic in the Performance Monitor Counters is faulty, and under certain timing
conditions, the overflow may remain undetected. In this case, the Overflow Flag Status register
(PMOVSR) is not updated as it should, and no interrupt is reported on the corresponding PMUIRQ
line.
It is important to notice that the Cycle counter is not affected by this erratum.
Projected Impact:
PMU overflow detection is not reliable.
Workarounds:
The main workaround for this erratum is to poll the performance counter. The maximum increment
in a single cycle for a given event is 2. Therefore, polling can be infrequent as no counter can
increment by more than 2^32 in fewer than 2 billion cycles.
If the main usage model for performance counters is collecting values over a long period, then
polling can be used to collect values (and reset the counter) rather than waiting for an overflow to
occur. Polling can be done infrequently and overflow avoided.
If the main usage model for performance counters relies on presetting the counter to some value
and waiting for an overflow to occur, then polling can be used to detect when an overflow event
has been missed. An overflow can be determined to have been missed if the unsigned value in the
counter is less than the value preset into the counter. Again, polling can be done infrequently
because of the number of cycles it would need for this check to fail. In the case that the erratum
was triggered and an overflow event was missed, that counter sample can be thrown away or the
true value can be reconstructed.
An alternative workaround is to configure two counters to be triggered by the same event,
staggering their initial count values by 1. This will result in the rollover being triggered by at least
counter.
This alternative workaround works for all Cortex-A9 events but the three following ones, due to
the fact these three events can increment by 2 in a single cycle:
- 0x68 – Instructions coming out of the core renaming stage
- 0x73 – Floating-point instructions
- 0x74 – NEON instructions
For these 3 events, only the first workaround is applicable to fix the defect.
Proposed Solution:
No fix scheduled
Linux BSP Status:
Software workaround is not needed because this erratum will not be encountered in normal device
operation. The Freescale Linux BSP does not support this optional profiling feature. Users may add
ERR003719
ARM/MP: 751469 — Overflow in PMU counters may not be detected
