ERR009219
Chip Errata for the i.MX 6Dual/6Quad and i.MX 6DualPlus/6QuadPlus, Rev. 6.1, 06/2016
NXP Semiconductors
91
Description:
Certain applications require the source clock of the LVDS Display Bridge (LDB) to be modified
to accommodate various display clock frequency requirements. The clock source can be modified
by programming an asynchronous clock multiplexer (CCM_CS2CDR[LDB_DIx_CLK_SEL]) in
software.
Asynchronous multiplexers or glitchy multiplexers, enable the clock to switch immediately after
the multiplexer select is changed. Because both clock sources to the multiplexer are asynchronous,
switching the clocks from one source to the other can cause a glitch to be generated, regardless of
the input clock source. This immediate switch of two asynchronous clock domains can cause the
output clock to glitch. If the input and output clocks are not gated, this clock glitch can propagate
to the logic that follows the clock multiplexer, causing the logic to behave unpredictably.
A clock gate has not been implemented after the asynchronous clock multiplexer for the
LDB_DI0_IPU clock and LDB_DI1_IPU clocks. Due to the absence of this clock gate on this
LDB_DIx_IPU clock path, a glitch generated when the clock source is switched, can lock up the
LDB divider causing a loss of the LDB_DIx_IPU clock under certain conditions.
Projected Impact:
Switching LDB clock sources on an asynchronous clock multiplexer without gating the input and
output clock can cause clock glitches to propagate to the logic that follows the clock multiplexers,
causing the logic to behave unpredictably. With an ungated input clock, under certain conditions
the clock divider in the LDB_DIx_IPU clock path can incorrectly lock up. This can therefore cause
a loss of the LDB_DIx_IPU clock which can result in a blank LVDS display screen in the user
application.
Workarounds:
The input and output clocks to the asynchronous clock multiplexer are required to be gated prior
to switching the source clock. The recommended software workaround is to shut down the clocks
to the asynchronous clock multiplexor (CS2CDR: LDB_DIx_CLK_SEL) by disabling the
respective PLLs and PFDs prior to performing the clock switch. After the clock switch is
performed the input and output clocks of the multiplexer are re-enabled. Users must ensure that the
PFDs are reset after the respective PLLs are locked. It is recommended to perform the LDB clock
switch early in the boot process to minimize the clocking impact.
Please refer to Engineering Bulletin EB821 : LDB Clock Switch Procedure and i.MX6
Asynchronous Clock Switching Guidelines for further details on the issue and recommended
software workaround procedure.
ERR009219
CCM: Asynchronous clock switching can cause unpredictable
behavior [i.MX 6Dual/6Quad Only]
