ERR004490
Chip Errata for the i.MX 6Dual/6Quad and i.MX 6DualPlus/6QuadPlus, Rev. 6.1, 06/2016
160
NXP Semiconductors
Description:
When the remote link partner enters Recovery.rcvrlock from the L0 state and transmits only two
TS1 Ordered Sets (OS), the core can sometimes miss the second TS1 OS and therefore, delay its
entry into Recovery.rcvrlock.
Conditions:
Scenario Setup:
• The remote link partner enters Recovery.rcvrlock from the L0 state and transmits only two TS1
OSs
• The remote link partner then unusually moves to ElecIdle and de-asserts the PIPE signal rxvalid
in Recovery.RcvrLock
• The expected response from the core is that it will transition to Recovery.rcvrlock on receipt of
the two TS1 OSs
• The core receives a SKP OS or EIEOS that was inserted between the two TS1 Ordered Sets.
Projected Impact:
Consequences:
• The core might miss the second TS1 OS
• Because the remote partner only sent two TS1 OSs, the core will not receive a second TS1 OS
and therefore, stays in L0
• The PHY detects a decode error and passes it to the core
• The core sends the error message to the remote link partner
• The core does not get a response from the remote partner and replays the message three times
• The replay timer rolls over (caused by unacknowledged ERR_CORR messages) and a link
retrain is requested.
• The core moves to recovery.
Workarounds:
None. This is an unusual verification setup, and in a real system the remote partner must keep
sending TS1 OSs in Recovery.RcvrLock and then the core will move to Recovery after receiving
2 TS1 OSs.
Proposed Solution:
No fix scheduled
ERR004490
PCIe: 9000514662—LTSSM delay when moving from L0 to recovery
upon receipt of insufficient TS1 Ordered Sets
