ERR004321
Chip Errata for the i.MX 6Dual/6Quad and i.MX 6DualPlus/6QuadPlus, Rev. 6.1, 06/2016
156
NXP Semiconductors
Description:
The PCIe base specification states that before the L1 state can be entered, the Retry buffer must be
empty.
For PM Directed L1 Entry
5.3.2.1. Entry into the L1 State
The Downstream component then waits until it receives a Link Layer acknowledgement for the
PMCSR Write Completion, and any other TLPs it had previously sent. The component must
retransmit a TLP out of its Data Link Layer Retry buffer if required to do so by Data Link Layer
15 rules.
For ASPM L1 Entry
5.4.1.2.1. Entry into the L1 State
The Downstream component must wait until it receives a Link Layer acknowledgement for the last
TLP it had previously sent (the retry buffer is empty). The component must retransmit 30 a TLP
out of its Data Link Layer Retry buffer if required by the Data Link Layer rules.
In Addition For Entry into The L0s State
5.4.1.1.1. Entry into the L0s State
No TLP is pending to transmit over the Link, or no FC credits are available to transmit any TLPs.
This can be interpreted as meaning the retry buffer should be empty. This is because it might be
necessary to retransmit a TLP over the link, until a TLP has been acknowledged. The core does not
wait for the retry buffer to be empty before commencing L0s or L1 entry.
Conditions:
Scenario Setup:
1. Transmit a TLP from the DWC_pcie core
2. Suppress Ack/Nak transmission from the Link Partner.
3. Initiate PM directed L1, ASPM L0s or ASPM L1 entry.
4. The core will enter the appropriate low power state, even though it still has TLPs in the retry
buffer.
Projected Impact:
Low power states are entered inappropriately.
ERR004321
PCIe: 9000470913—Power Management Control: Core might enter
L0s/L1 before Retry buffer is empty
