ERR009596
Chip Errata for the i.MX 6Dual/6Quad and i.MX 6DualPlus/6QuadPlus, Rev. 6.1, 06/2016
140
NXP Semiconductors
Description:
The ARCR_GUARD bits of MMDC Core AXI Re-ordering Control register (MMDC_MAARCR)
are used to ensure better DDR utilization while preventing starvation of lower priority transactions.
After reordering is performed on previous read/write DDR transactions, the specific outstanding
transaction will first obtain the maximum score in “dynamic score mode" and then wait for
additional ARCR_GUARD count before achieving the highest priority. Due to a design issue, the
ARCR_GUARD counter doesn't count up to the pre-defined value in the ARCR_GUARD bit field
as expected. Therefore, the aging scheme optimizes the transaction reordering only up to the
default aging level (15) and assigns a highest priority tag to the outstanding transaction.
Projected Impact:
The aging scheme optimizes the transaction reordering only up to the default aging level (15). No
functional issues have been observed with an incorrect setting.
Workarounds:
Software should always program the ARCR_GUARD bits as 4'b0000. That means the accesses
which have gained the maximum dynamic score will always become the highest priority after
achieving the default highest aging level (15).
Proposed Solution:
No fix scheduled
Linux BSP Status:
Software workaround not implemented in Linux BSP. Functionality or mode of operation in which
the erratum may manifest itself is not used.The Freescale Linux BSP releases leave the
ARCR_GUARD bits at the default value of 4'b0000.
ERR009596
MMDC: ARCR_GUARD bits of MMDC Core AXI Re-ordering Control
register (MMDC_MAARCR) doesn't behave as expected
