FXTH870xD
Sensors
Freescale Semiconductor, Inc.
87
11
Periodic Wakeup Timer
The periodic wakeup timer (PWU) generates a periodic interrupt to wakeup the MCU from any of the STOP modes. It also has
an optional periodic reset to restart the MCU. It is driven by the LFO oscillator in the RTI module which generates a clock at a
nominal one millisecond interval. The LFO and the wakeup timer are always active and cannot be powered off by any software
control. The control bits are set so that there is either a periodic wakeup, a periodic reset, or both a wakeup interrupt and a
periodic reset. No combination of control bits will disable both the wakeup interrupt and the periodic reset. In addition, there is no
hardware control that can mask a wakeup interrupt once it is generated by the PWU.
11.1
Block Diagram
The block diagram of the wakeup timer is shown in
Figure 60
. This consists of a programmable prescaler with 64 steps that can
be used to adjust for variations in the value of the LFO period. Finally there are two cascaded programmable 6-bit dividers to set
wakeup and/or reset time intervals.
Figure 60. Wakeup Timer Block Diagram
The wakeup divider (PWUDIV) register selects a division of the incoming 1 ms clock to generate a wakeup clock, WCLK. The
WCLK frequency can be calibrated against the more precise external oscillator using the TPMS_LFOCOL firmware subroutine
as described in
. This subroutine turns on the RFM crystal oscillator and feeds a 500 kHz clock to the TPM1 for one
cycle of the LFO. The measured time is used to calculate the correct value for the WDIV[5:0] bits for a WCLK period of 1 second.
The TPMS_LFOCOL subroutine cannot be used while the RFM is transmitting or the TPM1 is being used for another task.
The wakeup time register (PWUSC0) selects the number of WCLK pulses that are needed to generate a wakeup interrupt to the
MCU. The periodic reset register (PWUSC1) selects the number of wakeup pulses that are needed to generate a periodic reset
of the MCU. Both the wakeup time counter and the periodic reset timer are incrementing counters that generate their interrupt or
reset when the desired count is reached and are then reset to zero. Reading the status of either of these counters will return a
zero content if done immediately after the interrupt or reset is generated.
If both the reset and the interrupt occur on the same clock cycle the reset will have precedence and the interrupt will not be
generated.
In order to prevent wakeup or reset from an extreme temperature event both the wakeup interrupt or periodic reset are disabled
if the thermal restart is activated and the TRO bit indicates that the device is still outside of the T
RESET
range. The wakeup and
periodic reset counters will still run. The state of these counters can be read using the PSEL bit in the PWUS register.
The wakeup interrupt (WUKI) cannot be masked by clearing the I-bit.
CONTROL
LOGIC
LFO
6-BIT
WAKEUP
WUF
PROGRAMMBLE
PRESCALER
WDIV[5:0]
WUT[5:0]
WUKI
PRST[5:0]
DIVIDER
6-BIT
PERIODIC
RESET
WCLK
RCLK
DIVIDER
PRF
PRST
WUFAK
TRO
PRFAK
TRE
Summary of Contents for FXTH870 D Series
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