NXP Semiconductors FXTH870 D Series, Manual

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FXTH870xD
Sensors
Freescale Semiconductor, Inc.
39
5.11.2 System Options Register 1 (SIMOPT1)
The following clock source and frequency selections are available using the system option register 1 as shown in Figure 22 .
Table 25. SRS Register Field Descriptions
Field Description
7
POR
Power-On Reset — This bit indicates reset was caused by the power-on detection logic. Because the internal supply voltage
was ramping up at the time, the low-voltage reset (LVR) status bit is also set to indicate that the reset occurred while the internal
supply was below the LVR threshold.
0
Reset not caused by POR
1 POR caused reset
6
PIN
External Reset Pin — This bit indicates reset was caused by an active-low level on the external reset pin if the device was in
either the STOP1 or RUN modes. This bit is not set if the external reset pin is pulled low when the device is in the STOP1 mode.
0
Reset not caused by external reset pin
1 Reset came from external reset pin
5
COP
Computer Operating Properly (COP) Watchdog — This bit indicates that reset was caused by the COP watchdog timer timing
out. This reset source may be blocked by COPE = 0.
0
Reset not caused by COP timeout
1 Reset caused by COP timeout
4
ILOP
Illegal Opcode — This bit indicates reset was caused by an attempt to execute an unimplemented or illegal opcode. The STOP
instruction is considered illegal if STOP is disabled by STOPE = 0 in the SOPT register. The BGND instruction is considered
illegal if ACTIVE BACKGROUND mode is disabled by ENBDM = 0 in the BDCSC register.
0
Reset not caused by an illegal opcode
1 Reset caused by an illegal opcode
3
ILAD
Illegal Address — This bit indicates reset was caused by an attempt to access either data or an instruction at an unimplemented
memory address.
0
Reset not caused by an illegal address
1 Reset caused by an illegal address
2
PWU
Programmable Wakeup — This bit indicates reset was caused by a PWU reset in run, WAIT, STOP4, and STOP3. After STOP1
exit, PRF in PWUCSI indicates PWU was the source of a wakeup.
0
Reset not caused by PWU.
1 Reset caused by PWU.
1
LVD
Low Voltage Detect — If the LVDRE and LVDSE bits are set and the supply drops below the LVD trip voltage, an LVD reset will
occur. This bit is also set by POR.
0
Reset not caused by LVD trip or POR.
1 Reset caused by LVD trip or POR.
0
Unused
Unused Bit — This bit always reads as a logical zero. Writes
$1802 Bit 7 6 5 4 3 2 1 Bit 0
R
COPE COPCLKS STOPE RFEN TRE TRH BKGDPE
W
RESET:
1 0 0 - 0 0 1 1
= Reserved
Figure 22. System Option Register 1 (SIMOPT1)
Table 26. SIMOPT1 Register Field Descriptions
Field Description
7
COPE
COP Enable — This control bit enables the COP watchdog. This bit is a write-once bit so that only the first write after reset is
honored. Reset sets the COPE bit.
0
COP Watchdog disabled.
1 COP Watchdog enabled.