NXP Semiconductors FXTH870 D Series, Manual

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FXTH870xD
Sensors
Freescale Semiconductor, Inc.
89
11.4 PWU Control/Status Register 1 - PWUCS1
The PWUSC1 register contains six bits to select the division of the incoming RCLK clock period and provide interrupt flag and
acknowledge bits as described in
Figure 63 .
5:0
WUT[5:0]
WUF Time Interval — These control bits select the number of WCLK clocks that are needed before the next wakeup interrupt
is generated. The count gives a range of wakeup times from 1 to 63 WCLK clocks.
Depending on the value of the bits for the WDIV[5:0] this time interval can nominally be from 1 to 63 seconds in 1 second steps.
Whenever the WUT[5:0] bits are changed the timeout period is restarted. Writing the same data to the WUT[5:0] bits has no
effect.
Writing zeros to all of the WUT[5:0] bits forces the wakeup divider to a value of $3F and disables the wakeup interrupt. However,
writing all zeros to the WUT[5:0] bits is inhibited if all of the PRST[5:0] bits are already cleared to zero. This prevents disabling
both the periodic wakeup and the periodic reset at the same time. See
Table 56 .
The WUT[5:0] bits are preset to a value of $3F (decimal 63) by any resets.
Table 56. Limitations on Clearing WUT/PRST
Control Bits State of Control Bits
Control Bits to be
Cleared
Resulting Action
Resulting Wakeup
Interrupt
Resulting Periodic
Reset
WUT[5:0]
non-zero
PRST[5:0]
Allowed Enabled
(1)
1. Using previous values.
Disabled
all zero Inhibited Disabled
(2)
2. Wakeup divider preset to $3F.
Enabled
(1)
PRST[5:0]
non-zero
WUT[5:0]
Allowed Disabled Enabled
(1)
all zero Inhibited Enabled
(1)
Disabled
$003A Bit 7 6 5 4 3 2 1 Bit 0
R
PRF 0
PRST[5:0]
W
PRFAK
RESET:
0 0 1 1 1 1 1 1
= Reserved
Figure 63. PWU Control/Status Register 1 (PWUCS1)
Table 57. PWUSC1 Register Field Descriptions
Field Description
7
PRF
Periodic Reset Flag — The PRF bit indicates when a periodic reset has been generated by the PWU. MCU writes to this bit
have no effect. This bit is cleared by writing a one to the PRFAK bit. This bit is cleared by a power on reset, but is unaffected by
other resets.
0
Periodic reset not generated or previously acknowledged.
1 Periodic reset generated.
6
PRFAK
Acknowledge PRF Interrupt Flag — The PRFAK bit clears the PRF bit if written with a one. Writing a zero to the PRFAK bit
has no effect on the PRF bit. Reading the PRFAK bit returns a zero. Reset has no effect on this bit.
0
No effect.
1 Clear PRF bit.
5:0
PRST[5:0]
Periodic Reset Time Interval — These control bits select the number of wakeup interrupts that are needed before the next
periodic reset is generated. The decimal count gives a range of periodic reset times from 1 to 63 wakeup interrupts. Depending
on the value of the bits for the WDIV[5:0] and WUT[5:0] this time interval can nominally be from 1 second to 66 minutes with
steps from 1 to 63 seconds. Whenever the PRST[5:0] bits are changed the timeout period is restarted. Writing the same data to
the PRST[5:0] bits has no effect.
Writing zeros to all of the PRST[5:0] bits forces the periodic reset to be disabled if at least one of the WUT[5:0] bits is set to a
one. This assures that there will be at least a wakeup interrupt. However, writing all zeros to the PRST[5:0] bits is inhibited if all
of the WUT[5:0] bits are already cleared to zero. This prevents disabling both the periodic wakeup and the periodic reset at the
same time. See
Table 56 . The PRST[5:0] bits are preset to a value of 63 by any resets.
Table 55. PWUSC0 Register Field Descriptions (continued)
Field Description